A scalable evolvable hardware processing array

Gallego, Ángel; Mora, Javier; Otero, Andrés; Torre, Eduardo de la; Riesgo, Teresa

doi:10.1109/reconfig.2013.6732266

Cited by 8 publications

(17 citation statements)

References 16 publications

(13 reference statements)

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“…Additionally, it removes the need of having a multiplexer at the input of every PE (except at the system input), thus again reducing the delay as well as the resource usage. Its simplicity is also an advantage in dynamically scalable systems such as [6].…”

Section: A Interconnection Topologiesmentioning

confidence: 99%

“…Additionally, they ensure that no other nets cross the reconfigurable area boundaries. The Dreams tool is used in [6] to implement a scalable systolic array of up to 8×7 PEs.…”

Section: *-Outmentioning

confidence: 99%

“…The first stage selects a row of the 3×3 pixel window, and the second one adds a certain amount of latency in order to shift the pixel to the left, since the window moves 1 pixel per clock cycle to the right. A similar approach has been previously done in [6]. The output selector is implemented as shown in Fig.…”

Section: B Processing Element Descriptionmentioning

confidence: 99%

“…The adoption of the LUT-based reconfiguration methodol ogy described in [2] has further compacted the array size, from the 5 CLBs per PE in [6] to only 2. Furthermore, this methodology has reduced the reconfiguration time about 20 times, providing much faster evolutions.…”

Section: Time Breakdownmentioning

confidence: 99%

“…The compacity of systolic arrays allows great processing speed, which has been tested to up to 500 MHz, as well as permitting the implementation of more processing arrays in the design, from one 8×7 array reported in [6] or three 4×4 arrays in [18], up to eight 8×8 arrays in a more reduced area. This parallelization, the increase of frequency of operation in the processing arrays, and the improved reconfiguration methodology allow testing over 80 000 filters per second (including reconfiguration and evaluation times for each solution).…”

Section: Time Breakdownmentioning

confidence: 99%

See 4 more Smart Citations

Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs

Mora

Otero

Torre

et al. 2015

2015 10th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

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Abstract-Evolvable hardware may be considered as the result of a design methodology that employs an evolutionary algorithm to find an optimal solution to a given problem in the form of a digital circuit.Evolutionary algorithms typically require testing thousands of candidate solutions, taking long time to complete. It would be desirable to reduce this time to a few seconds for applications that require a fast adaptation to a problem. Also, it is important to consider architectures that may operate at high clock speeds in order to reach very speed-demanding situations.This paper presents an implementation on an FPGA of an evolvable hardware image filter based on a systolic array architecture that uses dynamic partial reconfiguration in order to change between different candidate solutions. The neighbor to neighbor connections of the array offer improved performance versus other approaches, like Cartesian Genetic Programming derived circuits. Time savings due to faster evaluation compensate the slower reconfiguration time compared with virtual reconfiguration approaches, but, at any rate, reconfiguration time has been improved also by reducing the elements to reconfigure to just the LUT contents of the configurable blocks.The techniques presented in this paper lead to circuits that may operate at up to 500 MHz (in a Virtex-5), filtering 500 megapixels per second, the processing element size of the array is reduced to 2 CLBs, and over 80 000 evaluations per second in a multiplearray structure in an FPGA permit to obtain good quality filters in around 3 seconds of evolution time.

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Section: A Interconnection Topologiesmentioning

confidence: 99%

“…Additionally, they ensure that no other nets cross the reconfigurable area boundaries. The Dreams tool is used in [6] to implement a scalable systolic array of up to 8×7 PEs.…”

Section: *-Outmentioning

confidence: 99%

Section: B Processing Element Descriptionmentioning

confidence: 99%

Section: Time Breakdownmentioning

confidence: 99%

Section: Time Breakdownmentioning

confidence: 99%

See 3 more Smart Citations

Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs

Mora

Otero

Torre

et al. 2015

2015 10th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

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On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming

Mora

Salvador

Torre

2018

Genet Program Evolvable Mach

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Evolvable hardware allows generating circuits adapted to specific problems by using an evolutionary algorithm (EA). Dynamic partial reconfiguration of FPGA LUTs allows making the processing elements (PEs) of these circuits small and compact, thus allowing large scale circuits to be implemented in a small FPGA area. This facilitates the use of these techniques in embedded systems with limited resources.The improvement on resource-efficient implementation techniques has allowed increasing the size of processing architectures from a few PEs to several hundreds. However, these large sizes pose new challenges for the EA and the architecture, which may not be able to take full advantage of the computing capabilities of its PEs.In this article, two different topologies-systolic array (SA) and Cartesian genetic programming (CGP)-are scaled from small to large sizes and analyzed, comparing their behavior and efficiency at different sizes. Additionally, improvements on SA connectivity are studied.Experimental results show that, in general, SA is considerably more resource-efficient than CGP, needing up to 60% fewer FPGA resources (LUTs) for a solution with similar performance, since the LUT usage per PE is 5 times smaller. Specifically, 10×10 SA has better performance than 5×10 CGP, but uses 50% fewer resources.

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