Accelerating the evolution of a systolic array-based evolvable hardware system

On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming

“…The described SA architecture can be implemented in a very compact size, which results in a very small resource usage and good timing behavior. A 24×24 SA uses 10 176 LUTs (not including the control logic), less than 15% of the LUTs available on a Xilinx Virtex-5 LX110T FPGA, and a 10×10 one can be implemented in 2000 LUTs (less than 3%), which would allow to put several SAs in parallel as is done in [25,26].…”

“…Regarding area: the SA [26] requires 16 LUTs and 8 flipflops for each PE (100% of the available reserved logic resources for each PE is used so no further reduction is possible) in Virtex-5 devices; the hybrid VRC-DPR approach [7] requires 8 LUTs and 8 flip-flops per PE for a set of approximate PEs in a Zynq-7000 device. Regarding speed: the SA [25,26] works at up to 500 MHz, the fastest work reported so far to the best of these authors knowledge, achieving 19 000 circuit reconfigurations and evaluations per second on a system with a single array or up to 139 000 with 12 arrays in parallel 5 ; the hybrid VRC-DPR approach [7] works at 300 MHz, which results in 8700 evaluations per second or up to 30 000 on 6 arrays.…”

“…The most up-to-date reports from these works, the SA [26], and the hybrid VRC-DPR approach [7], are further analyzed considering area and maximum operating frequency achieved, thus evolution speed. Regarding area: the SA [26] requires 16 LUTs and 8 flipflops for each PE (100% of the available reserved logic resources for each PE is used so no further reduction is possible) in Virtex-5 devices; the hybrid VRC-DPR approach [7] requires 8 LUTs and 8 flip-flops per PE for a set of approximate PEs in a Zynq-7000 device.…”

“…This section details the SA implementation (the CGP counterpart will be discussed in section 5), and additionally describes the PE architecture that will be used in this case study for both SA and CGP implementations. The SA version of the filter has been implemented on a Xilinx Virtex-5 LX110T FPGA, which is later used to perform the tests, relying on DPR of LUTs through the ICAP of this FPGA to change the functionality of PEs as described in [26].…”

“…The filter is based on an SA with a size of 24×24 PEs, which is able to emulate smaller sizes by leaving some of its PEs unused. These PEs are implemented by directly instantiating LUTs with fixed positions on the FPGA, which allows changing their functionality by modifying the LUT configuration through DPR, as described in previous work [25,26].…”