Fault Classification for SRAM-Based FPGAs in the Space Environment for Fault Mitigation

In this work, Field Programmable Gate Array (FPGA) reconfigurability is exploited to realize autonomous fault recovery in mission-critical applications at runtime. The proposed Netlist Driven Evolutionary Refurbishment (NDER) technique utilizes design-time information from the circuit netlist to constrain the search space of the algorithm by up to 98.1% in terms of the chromosome length representing reconfigurable logic elements. This facilitates refurbishment of relatively large-sized FPGA circuits as compared to previous works. Hence, the scalability issue associated with Evolvable Hardware based refurbishment is addressed and improved. Experiments are conducted with multiple circuits from the MCNC benchmark suite to validate the approach and assess its benefits and limitations.Successful refurbishment of the apex4 circuit having a total of 1252 LUTs with 10% spares is achieved in as few as 633 generations on average when subjected to simulated randomly-injected single stuck-at faults. Moreover, the use of design-time information about the circuit undergoing refurbishment is validated as means to increase the tractability of dynamic evolvable hardware techniques.

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“…An algorithm is proposed in [34] which can be utilized to classify hard faults occurring in SRAM-based FPGAs.…”

Section: B Other Techniques For Refurbishment Of Reconfigurable Hardmentioning

confidence: 99%

Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

Ashraf

DeMara

2013

IEEE Trans. Comput.

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“…The problem has been investigated in [1], [2], and [3]. The work presented in [1] proposes only a rough and not evaluated algorithm, since the focus is on the design of the overall engine managing fault tolerance.…”

Section: Related Workmentioning

confidence: 99%

“…The reliability of the engine is guaranteed by periodically reading its configuration data, that is an expensive operation and subject to errors. The same authors later propose a detailed and refined version of the classification algorithm in [2]. In both approaches, the classification of the fault affecting a portion of the FPGA is based on the analysis of the relative and absolute frequency of the detected faults; if a portion of the FPGA is affected by a fault more frequently than the others, then the absolute frequency is analyzed, by taking into account the whole history of faults.…”

Section: Related Workmentioning

confidence: 99%

“…The algorithm has been tested by simulating the behavior of 4 systems in the space environment, where recoverable faults are caused by radiations without destructive effect (Single Event Upset, SEU), and non-recoverable faults are caused by radiations' accumulation (Total Ionizing Dose, TID) and device aging (Time Dependent Dielectric Breakdown, TDDB, and Electromigration, EM) [2]. Ten-year long missions at three different orbits have been envisioned: Low-Earth Orbit (LEO), Polar orbit, and Medium Earth Orbit (MEO).…”

Section: A Experimental Evaluationmentioning

confidence: 99%

“…Our algorithm has been compared with the contributes proposed in [4], [3], and [2]. No comparison with the work presented in [1] could be performed since no indication for setting the parameters of the algorithm was provided.…”

Section: B Comparison With Related Workmentioning

confidence: 99%

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A reliable fault classifier for dependable systems on SRAM-based FPGAs

Bolchini

Sandionigi

Fossati

et al. 2011

2011 IEEE 17th International on-Line Testing Symposium

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This paper presents an algorithm for the discrimination of faults in FPGAs based on their recovery possibility; some faults can be recovered by reconfiguring the faulty part of the device, others have a destructive effect. After classification has been carried out, the suitable fault recovery strategy is applied, with the final aim of enabling the exploitation of FPGAs, in particular SRAM-based ones, for critical applications, such as the ones in the space environment. In this scenario, we investigate the reliable implementation of the fault classification algorithm, that can be so integrated in an overall reliable system.

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Dependability Threats

Bolchini¹,

Michael²,

Miele³

et al. 2017

Dependable Multicore Architectures at Nanoscale

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The increasing diversity, density, and complexity of electronic devices is enabling the so-called digital revolution with the evident pervasive presence of electronics in everybody's lives. The benefits of this ubiquitous presence are impressive and widespread: from the constant improvement of productivity in the workplace to the societal impact of a constantly connected and sharing community.Whatever is the considered scenario, all this incredible progress has been relying on the assumption that the devices can be depended on in their application and for their purposes. The foundations for this assumption are based on a constant work behind the scenes of the technical and scientific community aimed at enhancing the dependability of the devices.Dependability is a broad term that summarizes several aspects of a system, which typically include availability, reliability, maintainability, safety, and security. All these aspects define whether and how the system will behave according to several requirements which can have different levels of priority based on the specific application. In particular, availability measures the amount of time a system is readily operating, reliability measures the continuity of the correct service, maintainability shows the ability of the system of being repaired and/or modified, safety targets the avoidance of catastrophic consequences in the case of lack of service, and finally security targets the resilience of a systems to threats caused by malicious third parties.There is an impressive amount of examples from technical literature and from the news about the dreadful consequences of the lack of dependability of an electronic system. Lack of dependability may have several negative consequences spreading from the loss of reputation of a manufacturer to the catastrophic loss of lives. Consider for example the automotive scenario, several cases of massive recalls were caused by issues in the electronic system: famously in one of such cases it was speculated that unintended acceleration causing loss of lives was to be ascribed to faults occurring in the drive-by-wire control modules.Apart from the loss of lives, the economic impact of unreliable hardware must also be taken into account. Depending on the particular product and application domain, the costs associated to lack of dependability can be extremely high:xiii

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Fault Classification for SRAM-Based FPGAs in the Space Environment for Fault Mitigation

Cited by 26 publications

References 3 publications

Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

A reliable fault classifier for dependable systems on SRAM-based FPGAs

Dependability Threats

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