A reliable fault classifier for dependable systems on SRAM-based FPGAs

Abstract

This paper presents an algorithm for the discrimination of faults in FPGAs based on their recovery possibility; some faults can be recovered by reconfiguring the faulty part of the device, others have a destructive effect. After classification has been carried out, the suitable fault recovery strategy is applied, with the final aim of enabling the exploitation of FPGAs, in particular SRAM-based ones, for critical applications, such as the ones in the space environment. In this scenario, we investigate the reliable implementation of the fault classification algorithm, that can be so integrated in an overall reliable system.

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

“…• definition of a design methodology for the realization of systems able to mitigate SE effects in the programmable part of SoPC platforms, by exploiting both classical and new fault detection and tolerance techniques, together with reconfiguration features [27], [28], [29]; and • definition of a suitable controller architecture for the management of the reconfiguration phase used to recover from the detected soft errors [30], [31].…”

Design of Hardened Embedded Systems on Multi-FPGA Platforms

“…Finally, by referring to the data reported in Bolchini et al [2011c], we can provide a rough estimation of the lifetime expected for the considered system. Without applying in general with the hardening strategies that can be adopted for the IRAs.…”

Increasing autonomous fault-tolerant FPGA-based systems' lifetime

“…The design approach proposed in this paper explores at designtime the different hardening and partitioning alternatives. We build upon our previous work to define an autonomous system able to mitigate permanent and transient fault; new hardening strategies are necessary with respect to those for the multi-FPGA or the transient-only scenarios ( [12], [13]), while we exploit the approaches presented in [14], [13], as discussed in the next sections.…”

“…It is worth noting that it is implemented on a rad-hard FPGA to guarantee its reliability and, consequently, the reliability of the overall system. When an error is signaled, the controller adopts the algorithm proposed in [14] to classify the kind of occurred fault (transient or permanent) and perform the suitable recovery action (scrubbing or relocation). In case of transient fault, only the faulty area is reconfigured, otherwise a total reconfiguration with a new bitstream is performed.…”