Fast timing analysis of clock networks considering environmental uncertainty

Wang, Hai; Yu, Hao; Tan, Sheldon X.-D.

doi:10.1016/j.vlsi.2011.03.001

Cited by 5 publications

(5 citation statements)

References 28 publications

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“…Various techniques have been proposed in the last three decades which try to reduce the test data by appropriately reusing the unspecified bits in the test data. Such techniques can be broadly classified as a) Linear decompressors and broadcast scan-based techniques and b) Code based techniques (Wang et al 2012). The categorization between the two majorly depends upon the fact that the former ones require the structural knowledge of the circuit under test while the code based don't.…”

Section: Analysis Of Existing Literaturementioning

confidence: 99%

An innovative two-stage data compression scheme using adaptive block merging technique

2020

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Test data has increased enormously owing to the rising on-chip complexity of integrated circuits. It further increases the test data transportation time and tester memory. The non-correlated test bits increase the issue of the test power. This paper presents a two-stage block merging based test data minimization scheme which reduces the test bits, test time and test power. A test data is partitioned into blocks of fixed sizes which are compressed using two-stage encoding technique. In stage one, successive blocks are merged to retain a representative block. In stage two, the retained pattern block is further encoding based on the existence of ten different subcases between the sub-block formed by splitting the retained pattern block into two halves. Noncompatible blocks are also split into two sub-blocks and tried for encoded using lesser bits. Decompression architecture to retrieve the original test data is presented. Simulation results obtained corresponding to different ISCAS'89 benchmarks circuits reflect its effectiveness in achieving better compression.

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Section: Analysis Of Existing Literaturementioning

confidence: 99%

An innovative two-stage data compression scheme using adaptive block merging technique

2020

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“…), write and read failures D w (w, t w ), write failure only D r (w, t r ), read failure only (11) where D(w, t) is the safety distance and t is the pulse-width for read or write operation. Due to the symmetrical structure, three transistor pairs are used to represent the 6T-SRAM.…”

Section: Problem Formulationmentioning

confidence: 99%

Reachability-Based Robustness Verification and Optimization of SRAM Dynamic Stability Under Process Variations

Song

Dinakarrao

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Therefore, the clock skew of a clock-tree branch is the sum of skews from all the grids it passes through S = i∈B k S i (24) where S i represents the skew from ith grid among set B k . Based on the derived sensitivity and skew function, a nonlinear optimization can be performed as follows.…”

Section: B Nonlinear Optimizationmentioning

confidence: 99%

“…Based on the derived sensitivity and skew function, a nonlinear optimization can be performed as follows. Substituting (19), (22), and (23) into (24), the clock-tree branch skew S converts to a quadratic function of inserted …”

Section: B Nonlinear Optimizationmentioning

confidence: 99%

“…Compared to clock tree in 2-D IC, the one in 3-D IC will experience much larger temperatures and stress gradients both vertically and horizontally. As signal TSVs are deployed to route 3-D clock tree over the entire 3-D chip, such nonuniform temperature differences can lead to a significant clock skew by electrical-thermal coupling of signal TSVs [24]- [26]. Such an electrical-thermal coupling becomes nonlinear when liner material is considered.…”

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Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical–Thermal–Mechanical Coupling

Sai

Shang

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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A robust physical design of 3-D IC requires investigation on through-silicon via (TSV). The large temperatures and stress gradients can severely affect TSV delay with large variation. The traditional physical model treats TSV as a resistor with linear electrical-thermal dependence, which ignores the fundamental device physics. In this paper, a physics-based electricalthermal-mechanical delay model is developed for signal TSVs in 3-D IC. With consideration of liner material and also stress, a nonlinear model is established between electrical delay with temperature and stress. Moreover, sensitivity analysis is performed to relate the reduction of temperature and stress gradients with respect to dummy TSVs insertion. Taking the design of 3-D clock tree as a case study, we have formulated a nonlinear optimization problem for clock-skew reduction. By allocating dummy TSVs to reduce the temperature and stress gradients, the clock skew introduced by signal TSVs and drivers can be minimized. A number of 3-D clock-tree benchmarks are utilized in experiments. We have observed that with the use of dummy TSV insertion, clock skew can be reduced by 61.3% on average when the accurate nonlinear electrical-thermal-mechanical delay model is applied.

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Fast timing analysis of clock networks considering environmental uncertainty

Cited by 5 publications

References 28 publications

An innovative two-stage data compression scheme using adaptive block merging technique

An innovative two-stage data compression scheme using adaptive block merging technique

Reachability-Based Robustness Verification and Optimization of SRAM Dynamic Stability Under Process Variations

Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical–Thermal–Mechanical Coupling

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