Fast test generation and partial testing for combinational logic circuits

Liu, J.

doi:10.1080/00207218708921025

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1989

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“…A corresponding proof of the algorithm is given. This paper was inspired by the general outline 'fast test generation' for conventional combinational circuits (Liu 1987).…”

Section: Introductionmentioning

confidence: 99%

Fast test generation for m-logic combinational circuits

Tabakow¹

1989

International Journal of Electronics

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A simple fast test generation algorithm by using the notion of M-difference is given for rn-logic combinational circuits (i.e. circuits which realize m-valued logic functions, rn 2 2). Without losing any generality, the proposed algorithm is defined only lor the case of primary input s-a-fault model. A corresponding proof of the algorithm is shown and several examples are given. Moreover a simplified version for m = 2 is illustrated. The above algorithms may be considered as some random (input space search) procedures and realized in a parallel way (e.g. by using a high speed modern supercomputer).

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“…A corresponding proof of the algorithm is given. This paper was inspired by the general outline 'fast test generation' for conventional combinational circuits (Liu 1987).…”

Section: Introductionmentioning

confidence: 99%

Fast test generation for m-logic combinational circuits

Tabakow¹

1989

International Journal of Electronics

View full text Add to dashboard Cite

show abstract

Fast test generation and partial testing for combinational logic circuits

Cited by 1 publication

References 5 publications

Fast test generation for m-logic combinational circuits

Fast test generation for m-logic combinational circuits

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