Fast test generation for m-logic combinational circuits

Abstract

A simple fast test generation algorithm by using the notion of M-difference is given for rn-logic combinational circuits (i.e. circuits which realize m-valued logic functions, rn 2 2). Without losing any generality, the proposed algorithm is defined only lor the case of primary input s-a-fault model. A corresponding proof of the algorithm is shown and several examples are given. Moreover a simplified version for m = 2 is illustrated. The above algorithms may be considered as some random (input space search) procedures and realized in a parallel way (e.g. by using a high speed modern supercomputer).