Fast statistical timing analysis by probabilistic event propagation

Liou, Jing-Jia; Cheng, Kwang-Ting; Kundu, Sandip; Krstić, A.

doi:10.1145/378239.379043

Cited by 113 publications

(72 citation statements)

References 9 publications

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“…One another approach we can think of is using the probabilistic events approach [16]. In this probabilistic event approach we have to discretize the inputs and evaluate the whole circuit.…”

Section: Problem Formulationmentioning

confidence: 99%

Timing Verification for Adaptive Integrated Circuits

Kumar¹,

Li²,

Shen³

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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An adaptive circuit can perform built-in self-detection of timing variations and accordingly adjust itself to avoid timing violations. Compared with conventional over-design approach, adaptive circuit design is conceptually advantageous in terms of power-efficiency. Although the advantage has been witnessed in numerous previous works including test chips, adaptive design is far from being widely used in practice.A key reason is the lack of corresponding timing verification support. We developed new timing analysis techniques to fill this void. A main challenge is the large runtime complexity due to numerous adaptivity configurations. We propose several pruning and reduction techniques and apply them in conjunction with statistical static timing analysis (SSTA). The proposed method is validated on benchmark circuits including the recent ISPD'13 suite, which has circuit as large as 150K gates. The results show that our method can achieve orders of magnitude speed-up over Monte Carlo simulation with about the same accuracy. It is also several times faster than an exhaustive application of SSTA.

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“…One another approach we can think of is using the probabilistic events approach [16]. In this probabilistic event approach we have to discretize the inputs and evaluate the whole circuit.…”

Section: Problem Formulationmentioning

confidence: 99%

Timing Verification for Adaptive Integrated Circuits

Kumar¹,

Li²,

Shen³

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

View full text Add to dashboard Cite

show abstract

“…Thus, constructing a circuit with output probability q is equivalent to determining the z i such that (6) evaluates to q. In the general case, depending on the values of p i and q, it is possible that q cannot be exactly realized by any circuit.…”

Section: A An Optimal Solutionmentioning

confidence: 99%

“…Algorithmic details for such analysis were first fleshed out by the testing community [5]. They have also found mainstream application for tasks such as timing and power analysis [6], [7].…”

mentioning

confidence: 99%

Transforming Probabilities With Combinational Logic

Qian

Riedel

Zhou

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Schemes for probabilistic computation can exploit physical sources to generate random values in the form of bit streams. Generally, each source has a fixed bias and so provides bits with a specific probability of being one. If many different probability values are required, it can be expensive to generate all of these directly from physical sources. This paper demonstrates novel techniques for synthesizing combinational logic that transforms source probabilities into different target probabilities. We consider three scenarios in terms of whether the source probabilities are specified and whether they can be duplicated. In the case that the source probabilities are not specified and can be duplicated, we provide a specific choice, the set {0.4, 0.5}; we show how to synthesize logic that transforms probabilities from this set into arbitrary decimal probabilities. Further, we show that for any integer n ≥ 2, there exists a single probability that can be transformed into arbitrary base-n fractional probabilities. In the case that the source probabilities are specified and cannot be duplicated, we provide two methods for synthesizing logic to transform them into target probabilities. In the case that the source probabilities are not specified, but once chosen cannot be duplicated, we provide an optimal choice. Index Terms-Logic synthesis, probabilistic logic, probabilistic signals, random bit streams, stochastic bit streams.

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“…Furthermore, these variations are increasing with each new generation of technology. Statistical Static Timing Analysis (SSTA) has been proposed to perform full-chip analysis of timing under such types of uncertainty, and has been the subject of intense research recently [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. The result of SSTA is the prediction of parametric yield at a given target performance for a design.…”

Section: Introductionmentioning

confidence: 99%

An accurate sparse-matrix based framework for statistical static timing analysis

et al. 2012

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Statistical Static Timing Analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important that the error introduced in SSTA be significantly smaller than the manufacturing variations being modeled. Achieving such accuracy requires careful attention to the delay models and to the algorithms applied. In this paper, we propose a new sparse-matrix based framework for accurate path-based SSTA, motivated by the observation that the number of timing paths in practice is sub-quadratic based on a study of industrial circuits and the ISCAS89 benchmarks. Our sparse-matrix based formulation has the following advantages: (a) It places no restrictions on process parameter distributions; (b) It embeds accurate polynomial-based delay model which takes into account slope propagation naturally; (c) It takes advantage of the matrix sparsity and high performance linear algebra for efficient implementation. Our experimental results are very promising.

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Fast statistical timing analysis by probabilistic event propagation

Cited by 113 publications

References 9 publications

Timing Verification for Adaptive Integrated Circuits

Timing Verification for Adaptive Integrated Circuits

Transforming Probabilities With Combinational Logic

An accurate sparse-matrix based framework for statistical static timing analysis

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