Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch

Kim, Jaeha; Jones, Kevin D.; Horowitz, Mark

doi:10.1109/tcsi.2009.2035418

Cited by 25 publications

(4 citation statements)

References 28 publications

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“…Since latched comparators are linear time-varying circuits, the following experiments are run using a post-layout periodic-steadystate simulation. The test-bench used for the presented results was inspired by [7] and [10]. Delay, offset, and power consumption are evaluated in a 151-point Monte Carlo simulation for a 11-point temperature variation in a range from −40 o C to 175 o C. The test-bench proposed in [7] is able to put latched comparator as close as possible of its metastable operation.…”

Section: Table 1: Transistor Sizing Of Sa and Dt Comparators (W X L)mentioning

confidence: 99%

“…The test-bench used for the presented results was inspired by [7] and [10]. Delay, offset, and power consumption are evaluated in a 151-point Monte Carlo simulation for a 11-point temperature variation in a range from −40 o C to 175 o C. The test-bench proposed in [7] is able to put latched comparator as close as possible of its metastable operation. In this case it achieves maximum delay for an input differential voltage equal to the comparator offset voltage.…”

Section: Table 1: Transistor Sizing Of Sa and Dt Comparators (W X L)mentioning

confidence: 99%

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A temperature-aware analysis of latched comparators for smart vehicle applications

Fonseca

Khattabi

Afshari

et al. 2017

Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands

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The challenges of the Internet of Things (IoT) in an urban environment are driven by smart vehicles which need to be able to efficiently sense and communicate with other nearby vehicles. Systemon-chip (SoC) applications in the automotive market have strict circuit performances and reliability requirements for a temperature range of up to 175 o C. This work proposes an analysis of latchedcomparators performance considering process variability and temperature variation. State-of-the-art StrongArm and Double-Tail comparators are designed using an XH018 technology. Post-layout simulation results are drawn in order to validate the proposed temperatureaware analysis. Besides the known advantages of the Double-Tail comparator, this work demonstrates that such a comparator has a serious drawback under harsh environments. At 175 o C, the Double-Tail presents a 3.1 ns worst case delay and 1.4 mV offset, while StrongArm shows 2.7 ns and 2.7 mV respectively. Moreover, the Double-Tail's input-referred noise achieves worst-case levels of 0.89 mV, the StrongArm's noise is below 0.4 mV. Therefore, the Double-Tail proved to be less reliable than the StrongArm and also foretells critical failure conditions in harsh environments. CCS CONCEPTS• Hardware Process, voltage and temperature variations; Analog and mixed-signal circuit synthesis;

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Section: Table 1: Transistor Sizing Of Sa and Dt Comparators (W X L)mentioning

confidence: 99%

Section: Table 1: Transistor Sizing Of Sa and Dt Comparators (W X L)mentioning

confidence: 99%

A temperature-aware analysis of latched comparators for smart vehicle applications

Fonseca

Khattabi

Afshari

et al. 2017

Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands

View full text Add to dashboard Cite

show abstract

“…RELATED WORK For logic, the use of RSM techniques in VLSI design for standard cell characterization is not new and its use was originally proposed in the late 80's by [12], [13]. Recently, the use of these regression modeling techniques raised interest again as an effective technique to cope with the explosion on the required process corners to capture the combined impact of local and global process variations [14].…”

Section: Fig 4 Overview Of the Memoryvam Approachmentioning

confidence: 99%

Variability aware modeling for yield enhancement of SRAM and logic

Miranda

Zuber

Dobrovolný

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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Anticipating silicon response in the presence or process variability is essential to avoid costly silicon re-spins. EDA industry is trying to provide the right set of tools to designers for statistical characterization of SRAM and logic. Yet design teams (also in foundries) are still using classical corner based characterization approaches. On the one hand the EDA industry fails to meet the demands on the appropriate functionality of the tools. On the other hand, design teams are not yet fully aware of the trade-offs involved when designing under extreme process variability. This paper summarizes the challenges for statistical characterization of SRAM and logic. It describes the key features of a set of prototype tools addressing that required functionality together with their application to a number of case studies aiming at enhancing yield at product level.

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“…Transistor-level mismatch is the primary obstacle to reaching a high yield rate for analog designs in deep submicron technologies. For example, due to an inverse-square-root-law dependence with the transistor area, the mismatch of CMOS devices nearly doubles for each process generation less than 90 nm [Masuda et al 2005;Kim et al 2007]. Since the traditional worst-case-or corner-case-based analysis is either so pessimistic that it sacrifices speed, power, and area, or too expensive for practical full-chip design, statistical approaches thereby become imperative to estimate the analog mismatch and performance variations [Pelgrom et al 1989].…”

Section: Introductionmentioning

confidence: 99%

Performance bound analysis of analog circuits in frequency- and time-domain considering process variations

Liu

Tan

Palma-Rodriguez

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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In this article, we propose a new performance bound analysis of analog circuits considering process variations. We model the variations of component values as intervals measured from tested chips and manufacture processes. The new method first applies a graph-based analysis approach to generate the symbolic transfer function of a linear(ized) analog circuit. Then the frequency response bounds (maximum and minimum) are obtained by performing nonlinear constrained optimization in which magnitude or phase of the transfer function is the objective function to be optimized subject to the ranges of process variational parameters. The response bounds given by the optimization-based method are very accurate and do not have the overconservativeness issues of existing methods. Based on the frequency-domain bounds, we further develop a method to calculate the time-domain response bounds for any arbitrary input stimulus. Experimental results from several analog benchmark circuits show that the proposed method gives the correct bounds verified by Monte Carlo analysis while it delivers one order of magnitude speedup over Monte Carlo for both frequency-domain and time-domain bound analyses. We also show analog circuit yield analysis as an application of the frequency-domain variational bound analysis.

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Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch

Cited by 25 publications

References 28 publications

A temperature-aware analysis of latched comparators for smart vehicle applications

A temperature-aware analysis of latched comparators for smart vehicle applications

Variability aware modeling for yield enhancement of SRAM and logic

Performance bound analysis of analog circuits in frequency- and time-domain considering process variations

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