A temperature-aware analysis of latched comparators for smart vehicle applications

Abstract

The challenges of the Internet of Things (IoT) in an urban environment are driven by smart vehicles which need to be able to efficiently sense and communicate with other nearby vehicles. Systemon-chip (SoC) applications in the automotive market have strict circuit performances and reliability requirements for a temperature range of up to 175 o C. This work proposes an analysis of latchedcomparators performance considering process variability and temperature variation. State-of-the-art StrongArm and Double-Tail comparators are designed using an XH018 technology. Post-layout simulation results are drawn in order to validate the proposed temperatureaware analysis. Besides the known advantages of the Double-Tail comparator, this work demonstrates that such a comparator has a serious drawback under harsh environments. At 175 o C, the Double-Tail presents a 3.1 ns worst case delay and 1.4 mV offset, while StrongArm shows 2.7 ns and 2.7 mV respectively. Moreover, the Double-Tail's input-referred noise achieves worst-case levels of 0.89 mV, the StrongArm's noise is below 0.4 mV. Therefore, the Double-Tail proved to be less reliable than the StrongArm and also foretells critical failure conditions in harsh environments. CCS CONCEPTS• Hardware Process, voltage and temperature variations; Analog and mixed-signal circuit synthesis;

Process-Voltage-Temperature Analysis of a CMOS-MEMS Readout Architecture

“…III). Addition simulations (not presented) show that the delay of the digital standard-cells increases over voltage-temperature variations confirming the results presented in the literature [12], [13]. Figure 6, obtained with steady-state analysis, illustrates the combined effect of these trends on the phase difference output metric.…”

“…Electronic sensitivity to environment variations is indeed high when process-voltagetemperature (PVT) variations are considered. Recent works have been interested in: the implications of small geometry effects [11], process-variability mitigation techniques for digital gates [12], the variation of comparator's delay over temperature [13], defining process-voltage-temperature (PVT) tolerant circuits [14], and minimizing thermal noise in CMOS amplifiers [15]. Furthermore, aforementioned system-level solutions require a differential architecture which are affected by mismatch issues between paths [16].…”

A Temperature-Aware Analysis of SAR ADCs for Smart Vehicle Applications

“…Both SA and DT comparators are designed using the XH018 180 nm technology which is measured and modeled for the −40 • C to 175 • C temperature range [8]. Table I presents transistor sizing for SA (see Fig 3(a)) and DT comparators (see Fig 3(b)) [7]. The layout of both comparator topologies is implemented using state of the art techniques.…”

“…There are two usual choices for latched comparators: the StrongArm (SA) and the Double-Tail (DT) architectures. Here, this paper overviews the temperature-aware analysis first presented in [7].…”

“…The aim is then to extend the temperature-aware analysis proposed by Fonseca et al [7] for performance variability in state-of-the-art SAR ADC which employs latched SA and DT comparators. This proposal overviews the temperature effects on MOS devices, covers the comparators design parameters in order to address performance variations (i.e.…”