Fast Montgomery modular multiplication and RSA cryptographic processor architectures

Mclvor, C.; McLoone, M.; McCanny, J.V.

doi:10.1109/acssc.2003.1291939

Cited by 72 publications

(50 citation statements)

References 10 publications

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“…They present a systolic array architecture resulting in a Montgomery based RSA implementation. More recent hardware implementations of Montgomery multiplication include the work by McIvor et al [9]. They use Carry Save Adders (CSAs) to perform the large word length additions required for Montgomery multiplication.…”

Section: Previous Workmentioning

confidence: 99%

See 1 more Smart Citation

Efficient pipelining for modular multiplication architectures in prime fields

Mentens

Sakiyama

Preneel

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation of the Montgomery algorithm, a more compact pipelined version is derived. The design makes use of 16-bit integer multiplication blocks that are available on recently manufactured FPGAs. The critical path is optimized by omitting the exact computation of intermediate results in the Montgomery algorithm using a 6-2 carry-save notation. This results in a high-speed architecture, which outperforms previously designed Montgomery multipliers. Because a very popular application of Montgomery multiplication is public key cryptography, we compare our implementation to the state-of-the-art in Montgomery multipliers on the basis of performance results for 1024-bit RSA.

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Section: Previous Workmentioning

confidence: 99%

“…This idea is in a way similar to our idea. In [9], the carry-save format is used in between modular multiplications to perform RSA, resulting in 5-2 CSA logic. In our implementation, instead we use 6-2 CSA logic, optimizing the internal loop in the Montgomery multiplication algorithm.…”

Section: Previous Workmentioning

confidence: 99%

Efficient pipelining for modular multiplication architectures in prime fields

Mentens

Sakiyama

Preneel

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

show abstract

“…There has been a lot of research looking into hardware architectures for fast Montgomery reduction and multiplication [20]. Montgomery modular multiplication however requires pre-and post-processing costs to convert values to and from the Montgomery domain.…”

Section: Montgomery Modular Multiplicationmentioning

confidence: 99%

Evaluation of Large Integer Multiplication Methods on Hardware

Rafferty¹,

O’Neill

Hanley³

2017

IEEE Trans. Comput.

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Abstract-Multipliers requiring large bit lengths have a major impact on the performance of many applications, such as cryptography, digital signal processing (DSP) and image processing. Novel, optimised designs of large integer multiplication are needed as previous approaches, such as schoolbook multiplication, may not be as feasible due to the large parameter sizes. Parameter bit lengths of up to millions of bits are required for use in cryptography, such as in lattice-based and fully homomorphic encryption (FHE) schemes. This paper presents a comparison of hardware architectures for large integer multiplication. Several multiplication methods and combinations thereof are analysed for suitability in hardware designs, targeting the FPGA platform. In particular, the first hardware architecture combining Karatsuba and Comba multiplication is proposed. Moreover, a hardware complexity analysis is conducted to give results independent of any particular FPGA platform. It is shown that hardware designs of combination multipliers, at a cost of additional hardware resource usage, can offer lower latency compared to individual multiplier designs. Indeed, the proposed novel combination hardware design of the Karatsuba-Comba multiplier offers lowest latency for integers greater than 512 bits. For large multiplicands, greater than 16384 bits, the hardware complexity analysis indicates that the NTT-Karatsuba-Schoolbook combination is most suitable.

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“…Even if it is not fully satisfactory, we decided to compare it with the best existing implementations (as we know) of the RSA algorithm [5,16] and elliptic curve processors [18,19]. Table 2 indicates that our implementation is definitely competitive with respect to other designs for equivalent security.…”

Section: Performancesmentioning

confidence: 99%

XTR Implementation on Reconfigurable Hardware

Peeters

Neve

Ciet³

2004

Lecture Notes in Computer Science

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Abstract.Recently, Lenstra and Verheul proposed an efficient cryptosystem called XTR. This system represents elements of F * p 6 with order dividing p 2 − p + 1 by their trace over F p 2 . Compared with the usual representation, this one achieves a ratio of three between security size and manipulated data. Consequently very promising performance compared with RSA and ECC are expected. In this paper, we are dealing with hardware implementation of XTR, and more precisely with Field Programmable Gate Array (FPGA). The intrinsic parallelism of such a device is combined with efficient modular multiplication algorithms to obtain effective implementation(s) of XTR with respect to time and area. We also compare our implementations with hardware implementations of RSA and ECC. This shows that XTR achieves a very high level of speed with small area requirements: an XTR exponentiation is carried out in less than 0.21 ms at a frequency beyond 150 MHz.

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Fast Montgomery modular multiplication and RSA cryptographic processor architectures

Cited by 72 publications

References 10 publications

Efficient pipelining for modular multiplication architectures in prime fields

Efficient pipelining for modular multiplication architectures in prime fields

Evaluation of Large Integer Multiplication Methods on Hardware

XTR Implementation on Reconfigurable Hardware

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