XTR Implementation on Reconfigurable Hardware

Abstract

Abstract.Recently, Lenstra and Verheul proposed an efficient cryptosystem called XTR. This system represents elements of F * p 6 with order dividing p 2 − p + 1 by their trace over F p 2 . Compared with the usual representation, this one achieves a ratio of three between security size and manipulated data. Consequently very promising performance compared with RSA and ECC are expected. In this paper, we are dealing with hardware implementation of XTR, and more precisely with Field Programmable Gate Array (FPGA). The intrinsic parallelism of such a device is combined with efficient modular multiplication algorithms to obtain effective implementation(s) of XTR with respect to time and area. We also compare our implementations with hardware implementations of RSA and ECC. This shows that XTR achieves a very high level of speed with small area requirements: an XTR exponentiation is carried out in less than 0.21 ms at a frequency beyond 150 MHz.

Authenticating Feedback in Multicast Applications Using a Novel Multisignature Scheme Based on Cubic LFSR Sequences

“…The N protocol [16] incurs the highest computation costs owing to the expensive bilinear pairing operations required in the signature/multisignature verification phase. Our proposed protocol CLFSR-MS uses extremely fast LFSR sequence operations [13,18] and can achieve the best computational efficiency. In the C protocol, both communication and computation costs increase with the depth of the tree and incurs the highest communication overhead (excluding overhead due to faults) per link.…”

“…The sequence terms are computed using the following two sequence operations [9], namely, (1) OP 1 : given an integer k and f e , compute the (ke)th state of the LFSR,s ke and (2) OP 2 : givens k ands e (both integers k and e need not be known), compute the (k + e)th state of the LFSR,s k+e . These sequence operations have been efficiently implemented in hardware [18]. We use the sequence operations to create/manipulate sequence terms in the proposed multisignature scheme.…”

Automatic Generation of Modular Multipliers for FPGA Applications

“…Therefore, the algorithm sketched by the above equations requires a small table. Carry-save implementations of (2) and (3) have, for example, been proposed by Jeong and Burleson [8], Kim and Sobelman [9], and Peeters et al [10]. Since these algorithms depend on the modulus M, they seem likely candidates for cryptographic hardware based on FPGAs: the reconfigurability of these devices allows one to optimize the architecture according to some parameters (e.g., the modulus) and to modify the hardware whenever they change.…”

Fast modular multiplication using parallel prefix adder

“…Modular multiplication is the most frequently used operation in these cryptographic applications which requires high area and power. Performance of cryptographic applications are decided by Area-Time complexity [1][2][3]. As a result, an efficient implementation becomes critical.…”