Fast disjoint transistor networks from BDDs

Abstract

In this paper, we describe different ways to derive transistor networks from BDDs. The use of disjoint pull-up (composed of PMOS transistors) and pull-down (composed of NMOS transistors) planes allows simplifications that result in shorter pull-up and pull-down transistor stacks. The reduced length of transistor stacks leads to the fastest implementation among the six different strategies evaluated to generate transistor networks from BDDs. Delay and area results are presented showing the impact of the proposed strategy.

Electrical Evaluation of Logic Network Generation Methods for On-the-Fly Supergate Design

“…The design on-the-fly approach allows multiple structures for a logic function implementation using Static CMOS Complex Gates (SCCG). For instance, a complex gate transistor network may consist of only series-parallel (SP) associations [7,12] or they could also benefit from non-seriesparallel (NSP) associations [13,14]. Fig.…”

“…In the literature, the number of transistors or stack (quantity of transistors associated in series) is commonly used as a metric to compare different designs [5,7,13,14]. The optimization of a topological metric may not imply better electrical behavior.…”

Transistor-level optimization of CMOS complex gates

“…In current VLSI design, the total number of transistors necessary to implement a logic gate is strongly related to the signal delay propagation, power consumption and area of integrated circuits (ICs) [1][2][3][4]. Transistor netlists are of special interest when designing standard cell libraries [5] or custom gates for improving a design [6].…”