Fast custom instruction identification by convex subgraph enumeration

Atasu, Kubilay; Mencer, Oskar; Luk, W.; Özturan, Can; Dündar, Günhan

doi:10.1109/asap.2008.4580145

Cited by 44 publications

(44 citation statements)

References 14 publications

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“…Unlike prior work, the techniques presented in this work do not rely on enumeration of maximal independent sets or maximal cliques. This work extends the work in [19], which describes a maximal convex subgraph enumeration algorithm with a proven upper bound on the size of the search space. The enumeration algorithm of [19] is explained in more depth, and additional search space reduction techniques are demonstrated.…”

Section: Introductionmentioning

confidence: 65%

“…This work extends the work in [19], which describes a maximal convex subgraph enumeration algorithm with a proven upper bound on the size of the search space. The enumeration algorithm of [19] is explained in more depth, and additional search space reduction techniques are demonstrated. The enumeration approach makes it possible to integrate any merit function for ranking the subgraphs.…”

Section: Introductionmentioning

confidence: 65%

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FISH: Fast Instruction SyntHesis for Custom Processors

Atasu

Luk

Mencer

et al. 2012

IEEE Trans. VLSI Syst.

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Abstract-This paper presents Fast Instruction SyntHesis (FISH), a system that supports automatic generation of custom instruction processors from high-level application descriptions to enable fast design space exploration. FISH is based on novel methods for automatically adapting the instruction set to match an application in a high-level language such as C or C. FISH identifies custom instruction candidates using two approaches: 1) by enumerating maximal convex subgraphs of application data flow graphs and 2) by integer linear programming (ILP). The experiments, involving ten multimedia and cryptography benchmarks, show that our contributed algorithms are the fastest among the state-of-the-art techniques. In most cases, enumeration takes only milliseconds to execute. The longest enumeration run-time observed is less than six seconds. ILP is usually slower than enumeration, but provides us with a complementary solution technique. Both enumeration and ILP allow the use of multiple different merit functions in the evaluation of data-flow subgraphs. The experiments demonstrate that, using only modest additional hardware resources, up to 30-fold performance improvement can be obtained with respect to a single-issue base processor.

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Section: Introductionmentioning

confidence: 65%

Section: Introductionmentioning

confidence: 65%

FISH: Fast Instruction SyntHesis for Custom Processors

Atasu

Luk

Mencer

et al. 2012

IEEE Trans. VLSI Syst.

Self Cite

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“…A design proposed in [8] applied to the base processor of Tensilica Xtensa and MicroBlaze processor to identify optimal instruction set from a give high level descriptions. This approach was based on ILP model and relaxes designer from the data bandwidth which is usually limited by FSL channels.…”

Section: Fig 3: Synthesis Of the Customized Hardware And Software Commentioning

confidence: 99%

Instruction Customization: A Challenge in ASIP Realization

Shrimal¹,

Jain²

2014

IJCA

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An Application Specific Instruction set Processors (ASIP) or alternatively known as customized processor is a processor designed for a particular application or for a set of applications. Earlier surveys show that though a significant research has been done for this most promising processor design technology, still approaches used in them are lacking in methodologies to define processor configuration based on the requirements of the applications. There are number of approaches claiming to design and synthesize ASIPs but they are facing many challenges. This paper is an attempt to find major challenges faced by them as well as the current state of these promising techniques adopted by the industry. This paper also analyzed their effort to know really what they could have achieved so far and identified what should be done to make these techniques successful. If some limitations can be removed soon, these techniques are going to expand in an explosive manner.

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“…A typical register file has two read ports and one write port, which limit the size of each ISE and the attainable speedup. Multi-cycle ISEs [12,10,14,15,1] overlap computation with I/O operations; however, the I/O interface remained a bottleneck. Several microarchitectural modifications have successfully improved input bandwidth, including shadow registers [5], register file clustering [7], and utilizing the pipeline forwarding logic [6].…”

Section: Related Workmentioning

confidence: 99%

Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions

Kluter

Burri

Brisk

et al. 2010

High Performance Embedded Architectures and Compilers

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Abstract. Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include Architecturally Visible Storage (AVS), compiler-controlled memories accessible exclusively to the ISEs. Unfortunately, the usage of AVS memories creates a coherence problem with the data cache. A multiprocessor coherence protocol can solve the problem, however, this is an expensive solution when applied in a uniprocessor context. Instead, we can solve the problem by modifying the cache controller so that the AVS memories function as extra ways of the cache with respect to coherence, but are not generally accessible as extra ways for use under normal software execution. This solution, which we call Virtual Ways is less costly than a hardware coherence protocol, and eliminate coherence messages from the system bus, which improves energy consumption. Moreover, eliminating these messages makes Virtual Ways significantly more robust to performance degradation when there is a significant disparity in clock frequency between the processor and main memory.

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Fast custom instruction identification by convex subgraph enumeration

Cited by 44 publications

References 14 publications

FISH: Fast Instruction SyntHesis for Custom Processors

FISH: Fast Instruction SyntHesis for Custom Processors

Instruction Customization: A Challenge in ASIP Realization

Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions

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