2010
DOI: 10.1007/978-3-642-11515-8_11
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Abstract: Abstract. Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include Architecturally Visible Storage (AVS), compiler-controlled memories accessible exclusively to the ISEs. Unfortunately, the usage of AVS memories creates a coherence problem with the data cache. A multiprocessor coherence protocol can solve the problem, however, this is an expensive solution when applied in a uniprocessor context. In… Show more

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Cited by 11 publications
(19 citation statements)
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References 16 publications
(23 reference statements)
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“…In the GARP [13], VEAL [8] and OneChip [7] systems, the compiler needs to insert some special instructions to ensure all preceding memory operations have completed before launching the custom instruction. Systems with architecturally visible storage (AVS) [5,14] also depend on the compiler for synchronization.…”
Section: Related Work and Our Contri-butionsmentioning
confidence: 99%
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“…In the GARP [13], VEAL [8] and OneChip [7] systems, the compiler needs to insert some special instructions to ensure all preceding memory operations have completed before launching the custom instruction. Systems with architecturally visible storage (AVS) [5,14] also depend on the compiler for synchronization.…”
Section: Related Work and Our Contri-butionsmentioning
confidence: 99%
“…The CI to be executed launches three memory operations: a read from location M 2 and writes to M 1 and M 3. For previous work [7,14], the CI needs to at least wait until the addresses of all preceding memory operations are computed before proceeding; this is enforced by inserting synchronization instructions before the CI. We overcome this limitation by modifying the core's microarchitecture.…”
Section: Issue 1: Maintaining Program Order For Memory Operationsmentioning
confidence: 99%
“…Way Stealing does not add extra memory elements to the system and, therefore, is memory coherent and consistent in presence of caches; unlike past solutions to the coherence problem for AVS-enhanced ISEs [19][20][21], Way Stealing requires more stringent boundary conditions. These conditions do not endanger its generality, but do require extensive, yet non-critical, changes to the processor pipeline and data cache.…”
mentioning
confidence: 99%
“…1(a) shows a RISC processor pipeline augmented with AVS-enhanced ISEs; the hardware realization of an ISE is called an Application Specific Custom Unit (ASCU), and it executes in parallel with the ALU stage of the pipeline. Without loss of generality, if Virtual Ways [19,21] is applied to ensure coherence between the processor's data cache and the AVS memory, then the tag portion of the AVS memory must be visible to the data cache (to provide coherence), while the data portion is only available to the ASCU.…”
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confidence: 99%
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