Fast and Parallel AAC Decoder Architecture for a Digital Radio Mondiale 30 Receiver

Ibraheem, Mohammed Shaaban; Hachicha, Khalil; Romain, Olivier

doi:10.1109/access.2017.2731902

Cited by 4 publications

(3 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Ibraheem et al investigated an FPGA based decoding of Advanced Audio Coding (AAC) focusing on a fast and parallel processing resulting in an achieved decoding rate of max. 30 Mbit/s [19]. Compared to LDACS the findings are only partially reusable since the pure FPGA-based implementation does not contain any mechanisms for transferring data between the software and hardware domains.…”

Section: Related Workmentioning

confidence: 99%

High Performance Implementation of Next Generation Aeronautical Communication Systems

Kurz

Gringinger

Rihacek

et al. 2022

IEEE Open J. Ind. Electron. Soc.

View full text Add to dashboard Cite

Current air traffic communication systems are mainly based on voice communication, with a newer digital communication technology called L-Band Digital Aeronautical Communication System (LDACS) being investigated in the Single European Sky Air Traffic Management Research (SESAR) project. An essential feature of this communication infrastructure is the encoding of data that guarantees reliable transport. While the encoding in the transmission path is straightforward, the decoding is computationally expensive due to the peculiarities of the convolutional codes used. As the target platform for the communication equipment is an embedded system, a proper system design is essential for the receiving path to ensure real-time processing. This paper therefore focuses on the hardware/software co-design of the functional system parts needed for decoding in the LDACS radio receiver. We describe the fundamental design considerations, followed by the actual implementation in form of software and FPGA-based hardware modules. Subsequently, the decoding solution was verified to prove a standard-compliant system. In an experimental validation, the actual system was fed with test data from a reference system. This allows conclusions to be drawn about system characteristics like data throughput, latency, and error correction. The resulting system demonstrates high-performance decoding that can exceed the desired requirements for quality and speed for use in the LDACS communication system.

show abstract

Section: Related Workmentioning

confidence: 99%

High Performance Implementation of Next Generation Aeronautical Communication Systems

Kurz

Gringinger

Rihacek

et al. 2022

IEEE Open J. Ind. Electron. Soc.

View full text Add to dashboard Cite

show abstract

“…The usage of FPGA-based systems in the telecommunication industry is widespread, with typical applications in the development of general transmission decoders [16,17], video decoders [18,19], security approaches like parity checks [20,21], satellite issues [22,23], and digital TV systems [24]. The modern usage of those devices includes machine learning proposals [25], cloud computing [26], and 5G communication networks [27].…”

Section: Related Workmentioning

confidence: 99%

Hardware Update through Digital TV Signals

et al. 2021

View full text Add to dashboard Cite

This paper presents a new hardware reconfiguration approach named hardware reconfiguration through digital television (HARD), which can update FPGA hardware modules based on digital TV (DTV) signals. Such a scheme allows several synthesized hardware cores (bitstreams) signaled and broadcast through open DTV signals via data streaming to be identified, acquired, decoded, and then used for system updates. Reconfiguration data are partitioned, encapsulated into private sections, and then sent in a carrousel fashion in order to be recovered by modified receivers. Service information content, specially designed for identifying and describing the characteristics of multiplexed hardware bitstreams, was added to the transmitted signal and provided all necessary information in the traditional DTV style. The receiver framework, in turn, checked whether those characteristics corresponded to its embedded reconfigurable devices and, if a match was found, it reassembled the related bitstreams and reconfigured the respective internal circuits. Experiments performed with an implementation of the proposed methodology confirmed its feasibility and showed that remounting and reconfiguration times were satisfactory and presented no blocking aspect. Finally, HARD can be used in several designs regarding intelligent reconfigurable devices, minimize device costs in the long term, and provide better hardware reuse.

show abstract

“…The MPEG-2's ADY is close to zero, which indicates that there have been almost no publications in this topic from 2016. Similarly, MPEG-4 has a low ADY of 0.3 documents/year, with research documents focused on the AAC (Advanced Audio Coding) implementation [787][788][789].…”

Section: Compression Standardsmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

View full text Add to dashboard Cite

Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

show abstract

Fast and Parallel AAC Decoder Architecture for a Digital Radio Mondiale 30 Receiver

Cited by 4 publications

References 16 publications

High Performance Implementation of Next Generation Aeronautical Communication Systems

High Performance Implementation of Next Generation Aeronautical Communication Systems

Hardware Update through Digital TV Signals

Field Programmable Gate Array Applications—A Scientometric Review

Contact Info

Product

Resources

About