High Performance Implementation of Next Generation Aeronautical Communication Systems

Abstract

Current air traffic communication systems are mainly based on voice communication, with a newer digital communication technology called L-Band Digital Aeronautical Communication System (LDACS) being investigated in the Single European Sky Air Traffic Management Research (SESAR) project. An essential feature of this communication infrastructure is the encoding of data that guarantees reliable transport. While the encoding in the transmission path is straightforward, the decoding is computationally expensive due to the peculiarities of the convolutional codes used. As the target platform for the communication equipment is an embedded system, a proper system design is essential for the receiving path to ensure real-time processing. This paper therefore focuses on the hardware/software co-design of the functional system parts needed for decoding in the LDACS radio receiver. We describe the fundamental design considerations, followed by the actual implementation in form of software and FPGA-based hardware modules. Subsequently, the decoding solution was verified to prove a standard-compliant system. In an experimental validation, the actual system was fed with test data from a reference system. This allows conclusions to be drawn about system characteristics like data throughput, latency, and error correction. The resulting system demonstrates high-performance decoding that can exceed the desired requirements for quality and speed for use in the LDACS communication system.

Rapid Prototyping and International Validation Activity for the L-Band Digital Aeronautical Communications System (LDACS)

“…Here, we discuss the differences between our approach and those of others [32], [33]. The three prototypes utilized Xilinx MPSoC as their signal processing module, but they adopted different software/hardware co-design approaches.…”

“…The memory in our design had only two ports for access, which limited the memory accesses to two at a time. If the code has sequential memory access, the pm [33] pm [1] pm [31] metric_calloc #0 metric_calloc #1 metric_calloc #63 metric_calloc #62 'HLS ARRAY PARTITION' pragma can be used to solve the memory bandwidth bottleneck issue.…”

“…However, the implementation is physical layer only, and real-time processing was not considered. In [33], a practical LDACS prototype was developed which considers end-to-end real-time communications using MPSoC. This very prototype was used to conduct the interoperability tests in Sec.…”

“…The design approaches taken in [33] and our prototype are similar. One of the differences is that their implementation is based on Linux OS, whereas ours is based on bare-metal (no-OS) development to ensure time-critical operations.…”

Design of Zigbee Adaptive Wireless Sensor Network Based on RSSI Predictive Value

“…A thorough analysis of resource usage, cost of equipment, quality of service, power consumption, immunity from interference 12 , we have opted to use the Zigbee CC2530 model as the hardware system, which features a CPU utilizing an 8051 core with flash memory capacities ranging from 32 to 256 KB and a transmission rate of 250 kbps. The system operates within the voltage range of 2-3.6 V, in the 2.4 GHz operating band, and functions on a standard protocol compliant with IEEE802.15.4.…”