Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs

Samal, Sandeep Kumar; Panth, Shreepad; Samadi, Kambiz; Saedi, Mehdi; Du, Yi; Lim, Sung Kyu

doi:10.1145/2593069.2593140

Cited by 43 publications

(19 citation statements)

References 6 publications

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“…Fortunately, the problem is less severe in current monolithic 3-D FPGAs than other 3-D ICs. The reason is that heat dissipation is already reduced with shortened interconnects; most of the heat would be generated at the bottom CMOS logic layer and even heat generated at the top would flow to the bottom substrate, which is usually attached to a heat sink [90]. To solve the thermal and other system level issues, considerations including both device technologies and architecture designs are necessary.…”

Section: Discussionmentioning

confidence: 99%

Monolithic 3-D FPGAs

et al. 2015

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| This paper reviews the recent developments in monolithic 3-D field-programmable gate arrays (FPGAs). Enabling technologies are covered. Three representative groups of monolithic 3-D FPGAs are discussed: ''normally off, instantly on'' FPGAs, FPGAs with 3-D switches, and FPGAs with 3-D configuration memory and pass transistors. The circuit designs and implementations of each group are presented and examined.

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Section: Discussionmentioning

confidence: 99%

Monolithic 3-D FPGAs

et al. 2015

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“…Thus, the thermal coupling within monolithic stacks is larger and more uniform than for TSV-based 3D ICs. This, in turn, calls for dedicated thermal management [21].…”

Section: Options For 3d Chip Stackingmentioning

confidence: 99%

Physical Design Automation for 3D Chip Stacks

Knechtel¹,

Lienig²

2016

Proceedings of the 2016 on International Symposium on Physical Design

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The concept of 3D chip stacks has been advocated by both industry and academia for many years, and hailed as one of the most promising approaches to meet ever-increasing demands for performance, functionality and power consumption going forward. However, a multitude of challenges has thus far obstructed large-scale transition from "classical" 2D chips to stacked 3D chips. We survey major design challenges for 3D chip stacks with particular focus on their implications for physical design. We also derive requirements for advances in design automation, such as the need for a unified workflow. Finally, we outline current promising solutions as well as areas needing further research and development. bly design kit; design standards 2. 3D-CHIP STACKING OPTIONS AND HIGH-LEVEL DESIGN CHALLENGES 3D-chip stacking falls into four categories (Fig. 2): (i) package stacking, (ii) interposer stacks, (iii) through-silicon via (TSV)based 3D ICs, and (iv) monolithic 3D ICs. Each option has its This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike International 4.0 License.

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“…The thickness and thermal properties of the various materials used are tabulated in Table 1. The structure of the chip (excluding package) is taken from [7]. From this table, we observe that the embedded graphite on the top of the chip, as well as the PCB at the bot- tom have much higher thermal conductivities in the lateral direction than in the vertical direction.…”

Section: Thermal Analysismentioning

confidence: 99%

Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications

Panth

Samadi

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Power delivery to the tier farthest away from the package in 3D VLSI is challenging. This is because the current provided by the package on the bottom is (1) first used by other tiers before it reaches the top, and (2) delivered using extremely small-size intra and inter-tier vias. Our solution is a tier partitioning method that assigns power hungry cells to the tier closer to the package, which is farther away from the heat spreader. Our study shows that this approach alleviates the IR-drop, power delivery network (PDN) resource usage, and power consumption in the top tier. Moreover, moving the cells to the bottom tier, unlike popular belief, does not cause any serious thermal issues. This is especially true in mobile applications, where heat is dissipated by both the heat spreader and printed circuit board. In summary, our tier-partitioning leads to 24.66% IR-drop reduction, 28.57% PDN resource reduction, and 4% wirelength reduction, with < 1 • C increase in temperature.

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Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs

Cited by 43 publications

References 6 publications

Monolithic 3-D FPGAs

Monolithic 3-D FPGAs

Physical Design Automation for 3D Chip Stacks

Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications

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