Fast and accurate programming method for multi-level NAND EEPROMs

Hemink, G.; Tanaka, Tomoharu; Endoh, Tetsuo; Aritome, S.; Shirota, R.

doi:10.1109/vlsit.1995.520891

Cited by 72 publications

(25 citation statements)

References 4 publications

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“…2 shows the V T cumulative distribution at the first read operation and for increasing t B up to 1 week, after cycling with t cyc = 0.6 h, T cyc =RT and PV to the highest V T level. In order to minimize RTN effects on the V T distribution during data retention experiments [17], the PV operation was performed by an incremental step pulse programming (ISPP) algoritm with loose step amplitude [18]- [20], resulting in the nearly gaussian distributions of Fig. 2.…”

Section: Experimental and Theoretical Backgroundmentioning

confidence: 99%

Investigation of the threshold voltage instability after distributed cycling in nanoscale NAND Flash memory arrays

Compagnoni

Miccoli

Mottadelli

et al. 2010

2010 IEEE International Reliability Physics Symposium

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This paper presents a detailed experimental investigation of the cycling-induced threshold voltage instability of deca-nanometer NAND Flash arrays, focusing on its dependence on cycling time and temperature. When the array is brought to a programmed state after cycling, instability mainly shows up as a negative shift of its threshold voltage cumulative distribution, increasing with time and resulting from partial recovery of cell damage created in the previous cycling period. The threshold voltage loss displays a strong dependence not only on the tunnel oxide electric field during retention, but also on the cycling conditions. In particular, performing cycling over a longer time interval or at higher temperatures delays the threshold voltage transients on the logarithmic time axis. The delay factor is studied as a function of the cycling duration and temperature on 60 and 41 nm technologies, extracting the parameter values required for a universal damage-recovery metric for NAND.

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Section: Experimental and Theoretical Backgroundmentioning

confidence: 99%

Investigation of the threshold voltage instability after distributed cycling in nanoscale NAND Flash memory arrays

Compagnoni

Miccoli

Mottadelli

et al. 2010

2010 IEEE International Reliability Physics Symposium

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“…The growing demand of high-density NVM for the portable computing and telecommunications market has encouraged serious interest in Flash memory with the capability of multilevel storage [38], [39] and lowvoltage operation [40]- [42]. Multilevel storage implies the capability of storing two bits in a single cell.…”

Section: Industry-standard Flash Cellsmentioning

confidence: 99%

Flash memory cells-an overview

et al. 1997

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“…In MLCs or TLCs, fine placement of the V T levels is needed because of the reduced distance between adjacent distributions (see Figure 2). This is achieved via an incremental step-pulse programming (ISPP) technique [40], in which fast pulses of increasing amplitude are used to inject a constant, controlled amount of charge onto the floating gate at each step, interleaved with program verify phases in which V T is monitored. Several refinements are applied to this basic concept in 8-or 16-level cells [38].…”

Section: Programmentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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Fast and accurate programming method for multi-level NAND EEPROMs

Cited by 72 publications

References 4 publications

Investigation of the threshold voltage instability after distributed cycling in nanoscale NAND Flash memory arrays

Investigation of the threshold voltage instability after distributed cycling in nanoscale NAND Flash memory arrays

Flash memory cells-an overview

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

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