Fast Algorithms for Thermal-Aware Floorplanning

Abstract

Thermal-aware°oorplanning is an e®ective way to solve the thermal problem in modern integrated circuit (IC) designs. Existing thermal-aware°oorplanning methods are all based on simulated annealing (SA), genetic algorithms (GAs) or linear programming (LP), which are quite time-consuming. In this paper, we propose two fast algorithms for thermal-aware°oorplanning, a greedy algorithm based on the less-°exibility-¯rst (LFF) principle and a hybrid algorithm combining the greedy algorithm and an SA-based re¯nement. The greedy algorithm can fast obtain a locally optimized°oorplan with reduced area and temperature. The hybrid method can get similar results compared with pure SA-based approaches but it is still much faster.

DOTFloor–A Diffusion Oriented Time-Improved Floorplanner for Macrocells

“…Here optimization has been obtained for chip area, wire length, and on-chip temperature. The author in [22] presents two fast thermal-aware algorithms, one greedy and the other SA-Greedy hybrid algorithm for optimizing area and temperature of nonslicing floorplan. Like [20], the complexity of temperature computation was also avoided in [22].…”

“…The author in [22] presents two fast thermal-aware algorithms, one greedy and the other SA-Greedy hybrid algorithm for optimizing area and temperature of nonslicing floorplan. Like [20], the complexity of temperature computation was also avoided in [22]. Instead of any temperature quantification in the objective function, hotspot minimization has been mechanized in [22] by forming groups containing one hot and three non-hot modules in each and further placing them in floorplan, such that a hot module remains surrounded by the three non-hot modules of its group.…”

“…Like [20], the complexity of temperature computation was also avoided in [22]. Instead of any temperature quantification in the objective function, hotspot minimization has been mechanized in [22] by forming groups containing one hot and three non-hot modules in each and further placing them in floorplan, such that a hot module remains surrounded by the three non-hot modules of its group. Authors in [23] have considered the area and peak power density (of a thermal zone) as metrics of optimization in floorplanning, but peak power density alone cannot account for the degree of hotness in a chip.…”

“…Authors in [23] have considered the area and peak power density (of a thermal zone) as metrics of optimization in floorplanning, but peak power density alone cannot account for the degree of hotness in a chip. The techniques presented in [20], [22], [23] are fast but do not consider the influence of the adiabatic die-boundary on the thermal characterization of a chip.…”