Multi-objective optimization for energy and heat-aware VLSI floorplanning using enhanced firefly optimization

Srinivasan, B.; Venkatesan, Ramarathnam

doi:10.1007/s00500-021-05591-x

Cited by 13 publications

(19 citation statements)

References 69 publications

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“…The performance results of HMAC-FO-MOP and HMAC-FO-VOP techniques are compared with the results obtained for LOA [1], BCSA [2], HPSOGA [3] and MOFO-FP [4] with various metrics called area used by circuits, required wire length and peak temperature generation. The results prove that the proposed algorithm reduces the area by 3.48%, the wire length by 0.64% and the temperature by 3.33% than the best existing methodologies.…”

Section: Results Analysismentioning

confidence: 99%

“…The proposed algorithms are implemented in MATLAB 2015b with 2.10 GHz Intel Core i5 processor, 8GB RAM, and Windows 10 platform. Experimental evaluation of HMAC-FO-MOP and HMAC-FO-VOP techniques and Line Optimization Algorithm (LOA) [1], B* tree Crossover Simulated Annealing (BCSA) algorithm [2], Hybrid Particle Swarm Algorithm -Genetic Algorithm (HPSOGA) [3] and Multi-Objective Firefly Optimization-based FloorPlanning (MOFO-FP) [4] are implemented with the input data set which is obtained from (https://s2.smu.edu/~manikas/Benchmarks/MCNC_Bench mark_Netlists.html). The existing and proposed techniques are simulated with the same software and hardware platform.…”

Section: Methodsmentioning

confidence: 99%

“…In [3], the hybridized PSO-GA (particle swarm optimization-genetic algorithm) algorithm was designed to generate temperature-aware floorplans. A new algorithm named MOFO-FP (multi-objective firefly optimization-based floorplanning) was designed in [4] to reduce the chip's energy consumption and hot spots.…”

Section: Introductionmentioning

confidence: 99%

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A Novel Multicriteria Optimization Technique for VLSI Floorplanning Based on Hybridized Firefly and Ant Colony Systems

et al. 2023

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In VLSI circuit design, physical design is one of the main steps in placing the circuit into the chip area. Floorplanning is a crucial step in the physical design of IC design, which generates a blueprint for the placement of circuit modules into the chip. A floorplanning step accepts a netlist as its input, given by the circuit-partitioning step of physical design. The floorplanning step generates optimal placements for the circuit modules. The netlist contains the modules' dimensions, size, and interconnect information. During the floorplan generation, the chip area, wire length required for connecting modules and the heat generated by the chips can be estimated. A good floorplan makes placements and routing simple. In order to improve the circuit performance by minimizing chip area, wire length, and peak temperature, it is essential to generate an optimized floorplan by developing metaheuristic optimization algorithms. A novel Hybridized Multicriteria Ant Colony and Firefly Optimization (HMAC-FO) technique is introduced to generate an optimized floorplan. The primary focus of HMAC-FO technique is to design a model for generating efficient floorplanning. The standard MCNC benchmark dataset has a number of modules with their connections. Firefly optimization is the main algorithm in HMAC-FO, which has been used in generating efficient floorplan with the optimized area, wire length and thermal. The firefly algorithm initially requires some number of solutions as the fireflies' population. In the firefly algorithm, usually, the populations are generated randomly. But, to improve the firefly optimization algorithm's performance and obtain better optimum results, the proposed technique uses ACO to generate the initial population, which are all optimal solutions. The firefly algorithm uses the set of optimal solutions as the initial population and generates the globally optimal result. The proposed technique has experimented with the standard MCNC benchmark circuits, and the results prove that the proposed algorithm reduces the area by 3.48%, the wire length by 0.64% and the temperature by 3.33% than the best existing methodology. The proposed methodology generates a good floorplan with all the required optimization, such as area, wire length and heat generation.

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Section: Results Analysismentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

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A Novel Multicriteria Optimization Technique for VLSI Floorplanning Based on Hybridized Firefly and Ant Colony Systems

et al. 2023

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“…Cellular automation consists of a regular lattice of layers. Each layer takes then possible values and is updated dynamically according to simple discrete steps and time [11]. In Cellular Automata (CA) model, lattice of cells and a set of rules governing their behavior were established.…”

Section: Cellular Automata (Ca)mentioning

confidence: 99%

“…There are numerous algorithms [11][12][13][14][15][16][17][18][19] for solving the 2D floor planning problem. As a result, the third dimension greatly widens the search space and provides extra computational complexity and limitations, such as the insertion of heat through silicon vias.…”

Section: Scholarly Articlesmentioning

confidence: 99%

Ca & Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design

2023

Preprint

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Designing a simplest architecture involves appropriate placement, which is often, regarded as a critical concerns of physical design engineers. Placement and routing of chips in automated manner is been research since decades and provides better predictive performance than manual procedures. However, most of the automated models operating under meta-heuristic optimization fails in obtaining optimal solution due to premature convergence and non-optimal placement of solutions. In this paper, we develop a novel meta-heuristic optimization method namely Cellular Automata (CA) and Satin Bowerbird Optimization (SBO) that combines Primal-dual lagrangian technique (SimPL) and Complex Primal dual lagrangian (ComPL) for attaining optimal placement and routing of chips. The process of CA and SBO optimization approach operates on obtaining optimized placement solutions from the SimPL and ComPL solutions. The combination of CA-SimPL, SBO-SimPL, CA-ComPL and SBO-ComPL is implemented on electronic design automation (EDA) tools with python simulator for pre-training and fine-tuning the optimization model. The simulation is conducted on a high-end computing system to test the computational time speed up ratio on different threads and half-perimeter wire length (HWPL). The results of simulation shows that the proposed models obtain increased performance with reduced computational time than other methods.

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Physical Architecture of Linear Feedback Shift Register Using Clock Tree Synthesis for Cyber-Physical System

Nisha

Nithya

Selvakumar

2023

Lecture Notes in Networks and Systems

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Multi-objective optimization for energy and heat-aware VLSI floorplanning using enhanced firefly optimization

Cited by 13 publications

References 69 publications

A Novel Multicriteria Optimization Technique for VLSI Floorplanning Based on Hybridized Firefly and Ant Colony Systems

A Novel Multicriteria Optimization Technique for VLSI Floorplanning Based on Hybridized Firefly and Ant Colony Systems

Ca & Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design

Physical Architecture of Linear Feedback Shift Register Using Clock Tree Synthesis for Cyber-Physical System

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Multi-objective optimization for energy and heat-aware VLSI floorplanning using enhanced firefly optimization

Cited by 13 publications

References 69 publications

A Novel Multicriteria Optimization Technique for VLSI Floorplanning Based on Hybridized Firefly and Ant Colony Systems

A Novel Multicriteria Optimization Technique for VLSI Floorplanning Based on Hybridized Firefly and Ant Colony Systems

Ca &amp; Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design

Physical Architecture of Linear Feedback Shift Register Using Clock Tree Synthesis for Cyber-Physical System

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Ca & Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design