Fan-Out Wafer-Level Packaging with highly flexible design capabilities

Kurita, Yasuo; Kimura, Takehiro; Shibuya, K.; Kobayashi, Hiroaki; Kawashiro, Fumiyoshi; Motohashi, Norikazu; Kawano, Motoharu

doi:10.1109/estc.2010.5642888

Cited by 42 publications

(4 citation statements)

References 9 publications

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“…Refs. [19,20], one of the challenges of chip-first (either die faceup or face-down) FOWLP and the key reasons for them to introduce the chip-last or RDL-first FOWLP is the production yield during the RDL process is low because the KGDs are already embedded. This is true only if the chip-last (RDL-first) FTI is fully functionally tested before the chip-to-wafer bonding.…”

Section: Reasons For Chip-last or Rdl-first According Tomentioning

confidence: 99%

“…During IEEE/ESTC2010 and ECTC2011, NEC (now Renesas) presented a couple of papers on system in wafer-level package (SiWLP) [19], and "RDL-first" FOWLP [20]. These papers are based on their SMArt chip connection with feed through interposer packaging technology for interchip wide-band data transfer [21,22] and 3D stacked memory integrated on logic devices [23][24][25][26][27].…”

Section: Introductionmentioning

confidence: 99%

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Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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Section: Reasons For Chip-last or Rdl-first According Tomentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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“…αρ αρ [4] interface the Represents 1 0 gas le compressib the Represents 0 gas le compressib the Represents 0…”

Section: Governing Equationsmentioning

confidence: 99%

“…RDL first process was first proposed by Yoichiro Kurita et al [4], which was invented to improve FO-WLP technology without RDL process yield loss. RDL first process flow, as shown in Fig.1, involved the following steps: (a) Sacrificial layer was deposited on glass wafer.…”

Section: Introductionmentioning

confidence: 99%

Mechanism of Moldable Underfill(MUF) process for fan-out wafer level packaging

Ding

et al. 2015

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)

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Increasing challenges are faced to ensure moldability with rapid advances in flip chip technology such as decreasing bump pitch and stand-off height, especially when commercial Moldable Underfill (MUF) is used. The conventional way to detect the voids is to use C-Scan or Thru-Scan to acquire the voids shape and location after MUF process. The whole MUF process is like a black box and the mechanism of the voids formation is unknown. However, in our study Ansys Fluent commercial software was used to track the transient transformation of the voids and made the whole process transparent. The melting front of epoxy molding compound (EMC) was tracked by volume of fluid (VOF) method. In the whole study, only one phase, EMC, is incompressible. The other phase, void, is regarded as the compressible material and complies idea gas law. An actual wafer with the array of flip chip packages including the bumps would demand a large amount of elements and very high computational resources. Our simulation shed light on solving this issue by the simplified modeling. Due to our simulation results shows that filling efficiency is location independent, 4 packages instead of fully populated hundreds of packages are used to carry out the simulations. Structured grids are used for each bump to achieve a better converge during the calculation.In the final part, the mechanism of MUF process is investigated. The results show that the voids will be minimized after the inner pressure and outer pressure reaches a balance. Form inner side, initial vacuum pressure is very critical; from outside, packing force is very critical. EMC

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Fan-in Wafer-Level Packaging Versus FOWLP

Lau

2018

Fan-Out Wafer-Level Packaging

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Fan-Out Wafer-Level Packaging with highly flexible design capabilities

Cited by 42 publications

References 9 publications

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Mechanism of Moldable Underfill(MUF) process for fan-out wafer level packaging

Fan-in Wafer-Level Packaging Versus FOWLP

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