Failure mechanisms of flash cell in program/erase cycling

Abstract

The impact of programlerase cycling on Flash memory cell is reviewed considering both performance degradation of the typical bit and the evolution of the erase threshold voltage distribution of the whole memory array. Emphasis is given to the failure mechanisms which affect Flash memory endurance: the erratic erase phenomenon is discussed with reference to the model recently reported in the literature and a new degradation mechanism, induced by parasitic drain stress conditions in program/erase cycling, is presented.

Flash memory cells-an overview

“…The high degree of testability allows the detection at wafer level of latent defects, which may cause single bit failures related to programming disturbs, data retention, and premature oxide breakdown, thus making Flash memories more reliable than full-featured EEPROM's at equivalent density [53]. Flash arrays are verified analyzing array disturbs and erase-threshold distribution.…”

“…A typical result of an endurance test on a single cell is shown in Fig. 25 [53]. As the experiment was performed applying constant pulses, the variations of program and erase threshold levels give a measure of oxide aging.…”

“…Fig. 26 shows the threshold voltage distribution for a 1-Mb Flash device [53]. The distribution seems to be Gaussian, but it is not symmetrical toward lower values.…”

“…26) represents a large population of cells that erase faster than typical bits. This population is too large to be attributed to extrinsic defects, and it is believed to be related to statistical fluctuations of oxide charge and to the structure of the injecting electrode [53]. Positive charges in the tunnel oxide and irregular polycrystal grains may induce a local increase of the electric field, thus enhancing current injection locally and making individual cells erase faster than average.…”

Reducing latency overhead caused by using LDPC codes in NAND flash memory

“…Flash memory P/E cycling causes damage to the tunnel oxide of floating gate transistors in the form of charge traps in the oxide and interface states [7][8][9], which directly results in memory cell threshold voltage shift and fluctuation and hence degrades memory device noise margin. Let N denote the number of P/E cycles that memory cells have gone through and N trap denote the density growth of either interface or oxide traps.…”