Failure mechanisms and optimum design for electroplated copper Through-Silicon Vias (TSV)

Liu, Xi; Qiao, Chen; Dixit, Pradeep; Chatterjee, Ritwik; Tummala, Rao; Sitaraman, Suresh K.

doi:10.1109/ectc.2009.5074078

Cited by 85 publications

(5 citation statements)

References 9 publications

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“…The relative permittivity of selected via insulation materials are listed in table 1. Furthermore, polymers can act as a buffer for thermo-mechanical stress that is caused by coefficient of thermal expansion (CTE) mismatches between the via metallization and the silicon bulk material [17,21,20,22]. As shown in table 1, the Young modulus of these polymers is typically two orders of magnitude lower as compared to silicon dioxide and silicon nitride.…”

Section: Cte Materialsmentioning

confidence: 99%

Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires

Fischer

Bleiker

Haraldsson

et al. 2012

J. Micromech. Microeng.

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Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the package and shorter internal signal lengths with lower capacitive, resistive and inductive parasitics. This paper presents a novel low-cost fabrication technique for metal-filled TSVs with very high aspect ratios (>20). Nickel wires are placed in via holes of a silicon wafer by an automated magnetic assembly process and are used as a conductive path of the TSV. This metal filling technique enables the reliable fabrication of through-wafer vias with very high aspect ratios and potentially eliminates characteristic cost drivers in the TSV production such as advanced metallization processes, wafer thinning and general issues associated with thin-wafer handling.

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Section: Cte Materialsmentioning

confidence: 99%

Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires

Fischer

Bleiker

Haraldsson

et al. 2012

J. Micromech. Microeng.

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“…The most popular TSVs are either copper filled or tungsten filled [8][9][10] for lowtemperature processing environment, or poly-Si filled [5,6] for IC compatibility. Although copper-filled TSVs offer very low resistance (typically m scale), their thermo-mechanical reliability is the main concern, which is due to the large difference in the coefficients of thermal expansion (CTE) of copper (17 ppm) and silicon (2.8 ppm) [11][12][13][14]. Also, being a non-IC compatible material, copper cannot be used in the front-end-of-line (FEOL) part of the CMOS process where the transistors are processed or in the high-temperature processing environment, such as for silicon radiation detectors, resonators, etc.…”

Section: D Integration and Through-silicon Viasmentioning

confidence: 99%

Fabrication and electrical characterization of high aspect ratio poly-silicon filled through-silicon vias

Dixit

Vehmas

Vähänen

et al. 2012

J. Micromech. Microeng.

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This paper presents the fabrication and the electrical characterization of poly-Si filled through-silicon vias, which were etched in a 180 μm thin silicon device wafer, bonded to a handle wafer by plasma activated oxide-to-silicon bonding. Heavily doped poly-Si was used as interconnection material, which was deposited by low-pressure chemical vapor deposition. Two different via geometries, i.e. stadium shaped, and circular shaped, were tried. Sputtered aluminum metallization layers as double-side redistribution lines and contact pads, were used. Both Kelvin structures and daisy chains were fabricated and their electrical resistances were measured. The electrical resistance of a single stadium-shaped via was measured to be about 24 . The electrical resistance was varying from 60 to 90 for two-vias daisy chains. Measured results indicate that this via-first technology can be used for varying range of sensor applications like microphone, oscillator, resonator, etc where CMOS compatibility and high temperature processing are the prime requirements.

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“…Many research institutions such as IBM, Intel, MIT and Samsung have initiated research on it. Multi-functional sensing modules based on 3D-TSV packaging are key components for the internet success of things proposed by IBM and CISCO [7,8]. 3D-TSV technology can be revolutionary in improving the properties of product, which will also be the main direction of packaging development [9].…”

Section: Introductionmentioning

confidence: 99%

A reliable Cu–Sn stack bonding technology for 3D-TSV packaging

Chen

Cai

et al. 2014

Semicond. Sci. Technol.

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In this paper, Cu-Sn stack bonding technology for 3D-TSV packaging was described; some key technologies such as TSV (through silicon via) formation, silicon wafer thinning, TSV electroplating and Cu-Sn multilayer stack bonding were introduced. First of all, some sample chips with TSV and Cu-Sn bonding pads were fabricated for stacking. Then, two kinds of stack bonding experiments with or without TSV were carried out, respectively. 3-die, 7-die, and 10-die stacks were bonded and assembled. Finally, the bonding strengths of 3D-TSV stacking were characterized by shear test and tensile test, and also the electrical properties, thermal properties and corrosion resistance of stacked module. All the test results suggested that the reliable stack bonding technology can be used for 3D integration applications.

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Failure mechanisms and optimum design for electroplated copper Through-Silicon Vias (TSV)

Cited by 85 publications

References 9 publications

Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires

Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires

Fabrication and electrical characterization of high aspect ratio poly-silicon filled through-silicon vias

A reliable Cu–Sn stack bonding technology for 3D-TSV packaging

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