Fabrication and electrical characterization of high aspect ratio poly-silicon filled through-silicon vias

Abstract

This paper presents the fabrication and the electrical characterization of poly-Si filled through-silicon vias, which were etched in a 180 μm thin silicon device wafer, bonded to a handle wafer by plasma activated oxide-to-silicon bonding. Heavily doped poly-Si was used as interconnection material, which was deposited by low-pressure chemical vapor deposition. Two different via geometries, i.e. stadium shaped, and circular shaped, were tried. Sputtered aluminum metallization layers as double-side redistribution lines and contact pads, were used. Both Kelvin structures and daisy chains were fabricated and their electrical resistances were measured. The electrical resistance of a single stadium-shaped via was measured to be about 24 . The electrical resistance was varying from 60 to 90 for two-vias daisy chains. Measured results indicate that this via-first technology can be used for varying range of sensor applications like microphone, oscillator, resonator, etc where CMOS compatibility and high temperature processing are the prime requirements.

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“…Shapes are usually obtained through the generation of wafers by photolithography, i.e., by polymerization of a photoresist or photosensitive material exposed to UV light through a patterned mask. Pattern refinement is obtained using deep reactive ion etching (DRIE) and tapered using the surface technology system inductive coupled plasma (STS-ICP) silicon etcher and oxide deposition (Tezcan et al, 2006;Dixit et al, 2012). Recently, spatial resolution of culture devices has been improved with the laser writing technique of 2-photon lithography with which 3D microstructures below 100 nm can be generated (Accardo et al, 2017;Lemma et al, 2019).…”

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“…Material deposition using evaporators [ 71 , 72 ] or chemical vapor deposition techniques such as LPCVD (Low Pressure Chemical Vapor Deposition) [ 73 , 74 ] or PECVD (Plasma Enhanced Chemical Vapor Deposition) [ 71 , 72 , 73 , 75 ] are used to form either protective layers on top of metalized electrodes or produce critical structures, like CMUT membranes itself. Some of the more complicated fabrication techniques involve specific processing steps such as chemical–mechanical polishing [ 76 , 77 ], deep reactive ion etching [ 78 ], local oxidation (LOCOS) process [ 79 , 80 ], and Oxford cryogenic etching of silicon [ 81 ].…”

A novel method for the fabrication of a high-density carbon nanotube microelectrode array

“…One common type of failure is voids, which are formed due to premature closing during the via-filling step. A few of solutions have been proposed in order to obtain void-free poly-Si vias, such as changing the trench design in order to get tapered vias [17] or carefully optimizing the CVD process parameters [18]. However, these suggested solutions are very challenging to implement.…”