2014
DOI: 10.1088/0268-1242/29/2/025003
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A reliable Cu–Sn stack bonding technology for 3D-TSV packaging

Abstract: In this paper, Cu-Sn stack bonding technology for 3D-TSV packaging was described; some key technologies such as TSV (through silicon via) formation, silicon wafer thinning, TSV electroplating and Cu-Sn multilayer stack bonding were introduced. First of all, some sample chips with TSV and Cu-Sn bonding pads were fabricated for stacking. Then, two kinds of stack bonding experiments with or without TSV were carried out, respectively. 3-die, 7-die, and 10-die stacks were bonded and assembled. Finally, the bonding … Show more

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Cited by 27 publications
(9 citation statements)
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“…叶焕等人 [152] 的研 究中 Sn9Zn0.5 Ga0.7Pr 并未出现类似的锡须抑制现象. [153] 对 3D TSV 芯片做了堆叠键合研究, 清华大学 Wu 等人 [154] 采用 Cu-Sn 表面活化键合实现 MEMS TSV 互连. 哈尔滨工业大学 Li 等人 [155] 采用超 声键合实现 Cu-Sn 3D 键合.…”
Section: 锡须问题unclassified
“…叶焕等人 [152] 的研 究中 Sn9Zn0.5 Ga0.7Pr 并未出现类似的锡须抑制现象. [153] 对 3D TSV 芯片做了堆叠键合研究, 清华大学 Wu 等人 [154] 采用 Cu-Sn 表面活化键合实现 MEMS TSV 互连. 哈尔滨工业大学 Li 等人 [155] 采用超 声键合实现 Cu-Sn 3D 键合.…”
Section: 锡须问题unclassified
“…[11,[13][14][15][16][17][18] Although these tests were performed to prove the technology for high-temperature applications, the shear strength of the tested samples was all carried out at room temperature. Mechanical integrity at temperature surpassing the melting temperature of Sn has long been predicted, but experimental verification is scarce.…”
Section: Solid-liquid Interdiffusion (Slid) Wafer-levelmentioning
confidence: 99%
“…The third trend concerns 3D integration and advanced packaging for which the stacking of different structures requires different level of interconnections, and therefore, a process with joining temperature sufficiently lower than the melting temperature should be performed several times on the same substrate [9][10][11][12].…”
Section: Introductionmentioning
confidence: 99%