Facilitating rapid first silicon debug

Balachandran, H.; Butler, K.M.; Simpson, Nelson

doi:10.1109/test.2002.1041814

Cited by 23 publications

(5 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Tech., 2010, Vol. 4 [3][4][5][6][7]: they enable the interaction with the program execution flow, incrementing control and observation abilities, either through structural or functional methodologies [6].…”

Section: Cross-fertilisation Principlesmentioning

confidence: 99%

“…An up front, careful planning of the test, diagnosis and debug strategies for a new circuit during system integration allows consequently faster production yield improvement and minimisation of final costs. Together with advanced pattern generation abilities, on-chip design-for-testability (DfT) hardware structures are mandatory for current electronic systems, and are often exploited for diagnosis, possibly with some enhancement [2]; focusing on the SoC yield ramp up problem, on-chip-specific silicon debug infrastructures have been successfully exploited in the last years [3][4][5][6][7]. This paper investigates common requirements and shared characteristics of test, diagnosis and silicon debug strategies for microprocessor-based SoCs; it presents an overview of the hardware and software aspects of these topics, and proposes an infrastructure intellectual property (I-IP) able to manage the execution of test, diagnosis and debug while taking advantage of the cross-fertilisation between the activities.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug

Bernardi

Grosso

Rebaudengo

et al. 2010

IET Computers &Amp; Digital Techniques

View full text Add to dashboard Cite

Semiconductor manufacturers aim at delivering high-quality new devices within shorter times in order to gain market shares. First silicon debug and diagnosis are important issues to be tackled in order to minimise the time-to-market and avoid expensive re-spins, while volume testing is necessary for guaranteeing acceptable quality levels. In this study, the authors propose an infrastructure intellectual property (I-IP) intended to be a companion for embedded processor cores. The proposed I-IP is an efficient, flexible, low cost and easy-toadopt solution for managing silicon debug, diagnosis and production test of microprocessor cores and of other cores in a system-on-chip (SoC), offering full support to the three domains of test, diagnosis and debug. A key characteristic of the proposed solution is that the requirements from the three domains are faced in an integrated manner, and the interface to the device during test, diagnosis and debug is a single one, supporting command-based interaction (instead of bit based). A prototypical design has been developed and integrated in an OGG Vorbis decoder SoC including a Leon2 microprocessor core, thus allowing a first practical evaluation about costs and benefits of the introduced I-IP-based approach. On this sample scenario, the key aspects in the process of testing, diagnosing and debugging a typical SoC are discussed.

show abstract

Section: Cross-fertilisation Principlesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug

Bernardi

Grosso

Rebaudengo

et al. 2010

IET Computers &Amp; Digital Techniques

View full text Add to dashboard Cite

show abstract

“…During the first silicon, the undetected bugs should be fixed because of the increasing cost of the mask. 3,4 To tackle the problem of bugs that exists even after the manufacturing test has been done, some of the techniques were developed for silicon validation to assist the design engineers efficiently. Reuse of IEEE standard (JTAG) is the first validation technique followed by the diligences with design for testability (DFT) structures.…”

Section: Introductionmentioning

confidence: 99%

Efficient signal selection using supervised learning model for enhanced state restoration

Rajendran

Muthaiah

2020

Computational Intelligence

View full text Add to dashboard Cite

The post-silicon validation and debug is the most important task in the contemporary integrated circuit design methodology. The vital problem prevailing in this system is that it has limited observability and controllability due to the minimum number of storage space in the trace buffer. This tends to select the signals prudently in order to maximize state reconstruction. In the reported works, to select and to restore the signals efficiently it is categorized into two types like low simulation with high-quality technique and high simulation with low-quality technique. In this work, a node-based combinational gate signal selection algorithm is proposed based on machine learning method that maximizes the state restoration capability. A significant improvement (80%) has made to achieve adequate simulation time with the high-quality associated with the state-of-the-art of supplementary methods.

show abstract

“…The second reason is that small-delay defects can become a reliability issue because the defect might be worsened during subsequent aging in the field and cause a failure of the device [7]. In addition, in order to improve the yield and reduce the time-to-market of VLSIs, design-related failures and performance limiters need to be identified and rectified during the first silicon debug [8]. However, the cost of testing and debugging for delay defects in modern highperformance chips by using external high-speed automatic test equipment (ATE) is very high.…”

Section: Introductionmentioning

confidence: 99%

Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement

Zhang

Namba

Ito

2014

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYIn recent VLSIs, small-delay defects, which are hard to detect by traditional delay fault testing, can bring about serious issues such as short lifetime. To detect small-delay defects, on-chip delay measurement which measures the delay time of paths in the circuit under test (CUT) was proposed. However, this approach incurs high test cost because it uses scan design, which brings about long test application time due to scan shift operation. Our solution is a test application time reduction method for testing using the on-chip path delay measurement. The testing with on-chip path delay measurement does not require capture operations, unlike the conventional delay testing. Specifically, FFs keep the transition pattern of the test pattern pair sensitizing a path under measurement (PUM) (denoted as p) even after the measurement of p. The proposed method uses this characteristic. The proposed method reduces scan shift time and test data volume using test pattern merging. Evaluation results on ISCAS89 benchmark circuits indicate that the proposed method reduces the test application time by 6.89∼62.67% and test data volume by 46.39∼74.86%.

show abstract

Facilitating rapid first silicon debug

Cited by 23 publications

References 13 publications

Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug

Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug

Efficient signal selection using supervised learning model for enhanced state restoration

Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement

Contact Info

Product

Resources

About