Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug

Abstract

Semiconductor manufacturers aim at delivering high-quality new devices within shorter times in order to gain market shares. First silicon debug and diagnosis are important issues to be tackled in order to minimise the time-to-market and avoid expensive re-spins, while volume testing is necessary for guaranteeing acceptable quality levels. In this study, the authors propose an infrastructure intellectual property (I-IP) intended to be a companion for embedded processor cores. The proposed I-IP is an efficient, flexible, low cost and easy-toadopt solution for managing silicon debug, diagnosis and production test of microprocessor cores and of other cores in a system-on-chip (SoC), offering full support to the three domains of test, diagnosis and debug. A key characteristic of the proposed solution is that the requirements from the three domains are faced in an integrated manner, and the interface to the device during test, diagnosis and debug is a single one, supporting command-based interaction (instead of bit based). A prototypical design has been developed and integrated in an OGG Vorbis decoder SoC including a Leon2 microprocessor core, thus allowing a first practical evaluation about costs and benefits of the introduced I-IP-based approach. On this sample scenario, the key aspects in the process of testing, diagnosing and debugging a typical SoC are discussed.

On‐chip support for software verification and debug in multi‐core embedded systems

“…Bernardi et al [40] proposed the addition of an infrastructure intellectual property (I‐IP) block to assist in silicon debug and testing of SoCs. This I‐IP block uses the SoC host processor to run software‐based self‐test (SBST) routines to test and debug the silicon.…”