Fabrication of SiO2/SiOx/SiOxNy Non-Volatile Memory with Transparent Amorphous Indium Gallium Zinc Oxide Channels

Nguyen, Hong Hanh; Nguyen, Van Duy; Trinh, Thanh Thuy; Jang, Kyungsoo; Baek, Kyunghyun; Raja, Jayapal; Yi, Junsin

doi:10.1149/1.3624573

Cited by 24 publications

(27 citation statements)

References 30 publications

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“…This is similar to the current behavior when the potential barrier is narrowed by the increase of the external field, which is a well‐known phenomenon called Fowler–Nordheim tunneling in the case of a heterostructure involving type‐II band alignment. This transition of the charge‐transport behavior depending on the applied voltage has been frequently observed in TMD‐based vdW heterojunctions …”

supporting

confidence: 58%

Direct Synthesis of a Self‐Assembled WSe₂/MoS₂ Heterostructure Array and its Optoelectrical Properties

et al. 2019

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Tremendous progress has been made in the investigation of 2D layered van der Waals (vdW) materials, which provide unique platforms for discovering fundamental condensed-matter phenomena. [1][2][3] In particular, heterostructures constructed from transition-metal dichalcogenides (TMD) have attracted considerable interest in the fields of physics and chemistry and for practical applications because they offer tunability of the properties, such as the band offset, carrier density, and polarity. [4][5][6][7][8] Several strategies for producing TMD-based heterostructures comprising semiconductor-semiconductor or metal-semiconductor junctions have been reported. [9][10][11] The first demonstrated TMD-based p-n junction was achieved via the mechanical stacking of microsized flakes. [4,5,12] Although the stacking method is a convenient approach for forming high-quality heterostructures for fundamental research, it relies on the probability of cleaving the bulk crystal, limiting the valuable area. For overcoming this limitation, chemical vapor deposition (CVD) has been recognized as a promising technique for forming a functional heterojunction, which can achieve not only high crystallinity but also direct synthesis of heterointerfaces with an atomically sharp boundary. [13][14][15][16][17] These TMD-based heterojunctions are pioneering advances in the fields of p-n diodes, light emitters, photodetectors, and field-effect transistors. [5][6][7][18][19][20][21][22][23] Despite such progress, it is still a grand challenging task to demonstrate the array of a hierarchical organization of the heterostructure with a controlled structure and spatial position. [24,25] In particular, the cross-aligned 1D matrix is considered as an ideal architecture for future electronics, as it significantly enhances device array integration in a limited space. [26][27][28] However, i) the complicated fabrication process involving high-temperature CVD that induces cross-contamination and ii) the unavoidable production of residues during the patterning process for defining the junction are critical hurdles for integrating the TMD heterostructure array on a large scale. [29] Recently, a novel solution-based approach has been exploited for synthesizing high-quality 2D TMD films, which is a simple and inexpensive method to control the number of layers and implement diverse structures. [30][31][32][33] Moreover, it can yield Functional van der Waals heterojunctions of transition metal dichalcogenides are emerging as a potential candidate for the basis of next-generation logic devices and optoelectronics. However, the complexity of synthesis processes so far has delayed the successful integration of the heterostructure device array within a large scale, which is necessary for practical applications. Here, a direct synthesis method is introduced to fabricate an array of self-assembled WSe 2 /MoS 2 heterostructures through facile solutionbased directional precipitation. By manipulating the internal convection flow (i.e., Marangoni flow) of the solution, ...

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supporting

confidence: 58%

Direct Synthesis of a Self‐Assembled WSe₂/MoS₂ Heterostructure Array and its Optoelectrical Properties

et al. 2019

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“…The charge trapping sites are observed in the all the conditions. In particular, SiO x having a high Si content shows a remarkably large number of Si-H bonds as well as HSi 3 O, HSi 2 O 2 , H 2 SiO 2 , and HSiO 3 at around 2000~2300 cm −1 [16,17], and as the GR increases, the absorptions around 2000–2300 cm −1 also increase. This implies that many Si phases and defects can exist in the Si-rich SiO X .…”

Section: Resultsmentioning

confidence: 99%

The Characteristics of Transparent Non-Volatile Memory Devices Employing Si-Rich SiOX as a Charge Trapping Layer and Indium-Tin-Zinc-Oxide

Park

Shin

2019

Nanomaterials

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We fabricated the transparent non-volatile memory (NVM) of a bottom gate thin film transistor (TFT) for the integrated logic devices of display applications. The NVM TFT utilized indium–tin–zinc–oxide (ITZO) as an active channel layer and multi-oxide structure of SiO2 (blocking layer)/Si-rich SiOX (charge trapping layer)/SiOXNY (tunneling layer) as a gate insulator. The insulators were deposited using inductive coupled plasma chemical vapor deposition, and during the deposition, the trap states of the Si-rich SiOx charge trapping layer could be controlled to widen the memory window with the gas ratio (GR) of SiH4:N2O, which was confirmed by fourier transform infrared spectroscopy (FT-IR). We fabricated the metal–insulator–silicon (MIS) capacitors of the insulator structures on n-type Si substrate and demonstrated that the hysteresis capacitive curves of the MIS capacitors were a function of sweep voltage and trap density (or GR). At the GR6 (SiH4:N2O = 30:5), the MIS capacitor exhibited the widest memory window; the flat band voltage (ΔVFB) shifts of 4.45 V was obtained at the sweep voltage of ±11 V for 10 s, and it was expected to maintain ~71% of the initial value after 10 years. Using the Si-rich SiOX charge trapping layer deposited at the GR6 condition, we fabricated a bottom gate ITZO NVM TFT showing excellent drain current to gate voltage transfer characteristics. The field-effect mobility of 27.2 cm2/Vs, threshold voltage of 0.15 V, subthreshold swing of 0.17 V/dec, and on/off current ratio of 7.57 × 107 were obtained at the initial sweep of the devices. As an NVM, ΔVFB was shifted by 2.08 V in the programing mode with a positive gate voltage pulse of 11 V and 1 μs. The ΔVFB was returned to the pristine condition with a negative voltage pulse of −1 V and 1 μs under a 400–700 nm light illumination of ~10 mWcm−2 in erasing mode, when the light excites the electrons to escape from the charge trapping layer. Using this operation condition, ~90% (1.87 V) of initial ΔVFB (2.08 V) was expected to be retained over 10 years. The developed transparent NVM using Si-rich SiOx and ITZO can be a promising candidate for future display devices integrating logic devices on panels.

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“…1,2 To develop the next-generation system-on-panel (SOP) applications, IGZO TFT nonvolatile memories have been studied as a TFT switch and memory element. [3][4][5][6][7] Various IGZO TFT memories with different charge storage media such as, metal nanocrystals (Pt, Au) 4,5 and dielectrics (SiO x , Si 3 N 4 , Al 2 O 3 ), 6,7 are explored. However, the high operating voltages, retention loss and cycling decay are the challenges.…”

Section: Introductionmentioning

confidence: 99%

Electrical characteristics of gallium–indium–zinc oxide thin-film transistor non-volatile memory with Sm₂O₃ and SmTiO₃ charge trapping layers

Her

Chen

et al. 2015

RSC Adv.

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Fabrication of SiO2/SiOx/SiOxNy Non-Volatile Memory with Transparent Amorphous Indium Gallium Zinc Oxide Channels

Cited by 24 publications

References 30 publications

Direct Synthesis of a Self‐Assembled WSe₂/MoS₂ Heterostructure Array and its Optoelectrical Properties

Direct Synthesis of a Self‐Assembled WSe₂/MoS₂ Heterostructure Array and its Optoelectrical Properties

The Characteristics of Transparent Non-Volatile Memory Devices Employing Si-Rich SiOX as a Charge Trapping Layer and Indium-Tin-Zinc-Oxide

Electrical characteristics of gallium–indium–zinc oxide thin-film transistor non-volatile memory with Sm₂O₃ and SmTiO₃ charge trapping layers

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Fabrication of SiO2/SiOx/SiOxNy Non-Volatile Memory with Transparent Amorphous Indium Gallium Zinc Oxide Channels

Cited by 24 publications

References 30 publications

Direct Synthesis of a Self‐Assembled WSe2/MoS2 Heterostructure Array and its Optoelectrical Properties

Direct Synthesis of a Self‐Assembled WSe2/MoS2 Heterostructure Array and its Optoelectrical Properties

The Characteristics of Transparent Non-Volatile Memory Devices Employing Si-Rich SiOX as a Charge Trapping Layer and Indium-Tin-Zinc-Oxide

Electrical characteristics of gallium–indium–zinc oxide thin-film transistor non-volatile memory with Sm2O3 and SmTiO3 charge trapping layers

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Direct Synthesis of a Self‐Assembled WSe₂/MoS₂ Heterostructure Array and its Optoelectrical Properties

Direct Synthesis of a Self‐Assembled WSe₂/MoS₂ Heterostructure Array and its Optoelectrical Properties

Electrical characteristics of gallium–indium–zinc oxide thin-film transistor non-volatile memory with Sm₂O₃ and SmTiO₃ charge trapping layers