Fabrication of InAs composite channel high electron mobility transistors by utilizing Ne-based atomic layer etching

Abstract

High electron mobility transistors ͑HEMTs͒ with InAs/ InGaAs composite channel were fabricated by employing low damage, highly selective Ne-based atomic layer etching ͑ALET͒ for the dry gate recess process. Ne-based ALET exhibited very high etch selectivity of InP over InAlAs which is suitable for dry gate recess process removing InP etch stop layer on top of InAlAs Schottky barrier layer. The plasma induced damage on the exposed InAlAs surface due to the ALET was much lower than that due to the conventional Ar-based reactive ion etching ͑RIE͒, which was verified by atomic force microscopy and Hall measurements. For further comparison, dc characteristics were compared for the two types of 0.3 m HEMTs fabricated by utilizing ALET and conventional RIE during the dry gate recess processes.

Overview of atomic layer etching in the semiconductor industry

“…5,14 Another proposal has been to replace Ar with other atoms that have lower sputtering yields since Ar is especially efficient at sputtering silicon due to the similar masses. Other bombarding particles such as neon 50,68,69,96 have been explored as well. More studies are needed to better understand the trade-offs in using different bombarding particles, and in managing any unintentional sputtering.…”

“…These include electron cyclotron resonance plasma, 33,39,56,62,86,87 helicon source plasma, 49,88 TCP, 6 capacitively coupled plasma, 5,60,89 and inductively coupled plasma. 90 Other types of energetic species have also been evaluated, including ion beams, 40,48 neutral beams, 35,[50][51][52]68,69,83,[91][92][93][94][95][96] and laser beams. 32,66,67,97,98 While specialized equipment certainly plays an integral part in basic understanding of ALE, it may be more practical to adapt conventional etching equipment for use in ALE.…”

Scalability of Sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications

“…2(b), which corresponds to an L g = 45 nm device. This is slightly different from the MBE-grown nominal barrier thickness of 11 nm, probably as a result of the finite etching selectivity of InP against InAlAs during Ar-based plasma [20]. Finally, device fabrication was completed by the evaporation and lift-off of Ti/Pt/Au (20/20/300 nm) Schottky gate metal stack.…”

Atomic Layer Etching: An Industry Perspective

“…They have demonstrated InP recess stopping on an InAlAs/InGaAs transistor channel. 3,4 The benefit of the ALEt process was observed by fabricating transistors with superior Hall mobilities relative to devices patterned with conventional plasma processes. They have also used a Ne neutral beam for ALEt of GaAs and demonstrated preservation of the surface stoichiometry, which was not achieved through a continuous ICP plasma etch.…”

“…The idealized sequence described in Figure 1a-1d enables formation of an anisotropic atomic layer removal of material. Several reports are present in the literature [2][3][4][5][6][7][8] where variations of the idealized flow have been successfully demonstrated. A requirement for this flow, and hence somewhat of a limitation, is that the modified surface layer released during the process in Figure 1c should be a stable volatile by-product so that it can be efficiently pumped out of the process chamber.…”