Atomic Layer Etching: An Industry Perspective

Carver, Colin T.; Plombon, John J.; Romero, Patricio E.; Suri, S. A. K; Tronic, Tristan A.; Turkot, R. B.

doi:10.1149/2.0021506jss

Cited by 134 publications

(128 citation statements)

References 25 publications

(42 reference statements)

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“…10,15 In this case one may need less directional etch conditions, and higher pressures in combination with dedicated microplasma sources may accomplish this. In the next section we will discuss the general trends in microplasma source design and miniaturization.…”

Section: Timescale Analysis For Convection Diffusion Deposition Andmentioning

confidence: 99%

“…When, in addition, the etch process is applied with a uniform ALD-based passivation by SiO 2 or alike rather than with CVD-based C 4 F 8 -based half-cycles, the anisotropy control and high fidelity pattern transfer can be improved in 2D and in 3D etching. Furthermore, in many FEOL and BEOL flowcharts any future spatial RIE modules can certainly be integrated with or into other spatial ALD-modules or pulsed CVD modules providing cost-effective and low-temperature or gap or via filling with liners, 53 seed/barrier layers, 10 etc. We note that the concept of spatial RIE etching can be applied in many more demanding application fields such as in the front-endof-line of the More Moore domain.…”

Section: Concluding Remarks and Outlookmentioning

confidence: 99%

“…38,39 Interestingly, and seemingly controversial, this also includes the need for tunable plasma process parameters to initiate isotropic desorption from and volatilization of the surface independent of its local orientation. 10,15 11. The development of dedicated (micro)plasma sources in general 40 and atmospheric pressure sources in particular to increase throughput, deposition rate and to reduce process temperature and gas consumption.…”

mentioning

confidence: 99%

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Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

Roozeboom

Bruele

Creyghton

et al. 2015

ECS J. Solid State Sci. Technol.

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Conventional (3D) etching in silicon is often based on the 'Bosch' plasma etch with alternating half-cycles of a directional Sietch and a fluorocarbon polymer passivation. Also shallow feature etching is often based on cycled processing. Likewise, ALD is time-multiplexed, with the extra benefit of half-reactions being self-limiting, thus enabling layer-by-layer growth in a cyclic process. To speed up growth rate, spatial ALD has been successfully commercialized for large-scale and high-rate deposition at atmospheric pressure. We conceived a similar spatially-divided etch concept for (high-rate) Atomic Layer Etching (ALEt). The process is converted from time-divided into spatially-divided by inserting inert gas-bearing 'curtains' that confine the reactive gases to individual injection slots in a gas injector head. By reciprocating substrates back and forth under such head one can realize the alternate etching/passivation-deposition cycles at optimized local pressures, without idle times needed for switching pressure or purging. Another improvement toward an all-spatial approach is the use of ALD-based oxide (Al 2 O 3 , SiO 2 , etc.) as passivation during, or gap-fill after etching. This approach, called spatial ALD-enabled RIE, has industrial potential in cost-effective back-endof-line and front-end-of-line processing, especially in patterning structures requiring minimum interface, line edge and fin sidewall roughness (i.e., atomic-scale fidelity with selective removal of atoms and retention of sharp corners). Today, the continuous doubling of the transistor count on planar microprocessor and memory chips in a two-year cadence has reached the point where Moore's Law (essentially an economic law) and Dennard's scaling (transistor and pitch dimensions) have approached their limits in 2D-scaling. The end of the planar device era was marked with the introduction in 2011 of the 22-nm Tri-Gate device.1,2 Figure 1 shows its design with gates surrounding the channel on three sides of vertical fins to improve gate delay.Today, at the emergence of the 10-nm technology node and the 50 th anniversary of Moore's Law, 3D device and integration solutions are being rapidly introduced both intra-chip, e.g., Gate-All-Around, 3 vertical NAND, 4 and inter-chip, e.g., 3D Through-Silicon Vias (TSVs). 5History of 3D etching.-Whereas the transistor design has been planar for most of its history, its periphery has been subjected to 3D design early on. One of the earliest 3D concepts has been the basic invention of 3D TSVs, already filed in 1958 by the famous W. Shockley, 6 cf. Fig. 2. Yet, in reality 3D Through-Silicon Via (TSV) technology took decades to accelerate the now rapidly growing stacked-chips and micro-electromechanical systems (MEMS) markets by enabling their interconnection in a 3D-integrated System-in-Package (i.e. the so-called 'More than Moore' domain). Today, the mainstream industrial technology for etching of both TSV and MEMS structures is ion-assisted etching or (Deep) Reactive Ion Etching. This method has become so ...

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Section: Timescale Analysis For Convection Diffusion Deposition Andmentioning

confidence: 99%

Section: Concluding Remarks and Outlookmentioning

confidence: 99%

mentioning

confidence: 99%

See 1 more Smart Citation

Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

Roozeboom

Bruele

Creyghton

et al. 2015

ECS J. Solid State Sci. Technol.

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“…Recently, atomic layer etching (ALE) technology has attracted much attention due to miniaturization and high integration of semiconductor devices . This ALE technology can process semiconductors more precisely than conventional reactive ion etching (RIE) and has advantages such as high etch selectivity, low surface damage, etc .…”

Section: Introductionmentioning

confidence: 99%

Anisotropic atomic layer etching of W using fluorine radicals/oxygen ion beam

Kim

Lee

et al. 2019

Plasma Processes & Polymers

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Atomic layer etching (ALE) has advantages such as precise thickness control, high etch selectivity, and no‐increase in surface roughness which can be applied to sub 10 nm semiconductor device fabrication. In this study, anisotropic ALE of tungsten (W), which is used as an interconnect layer and gate material of semiconductor devices, was investigated by sequentially exposing to F radicals by NF3 plasma to form a WFy layer and following exposure to an oxygen ion beam to remove the WFy layer by forming volatile WOxFy at room temperature. A wide ALE window of F radical adsorption time of ( ≥ 10 s/cycle) and Ox+ ion desorption time of (10 ≤ t ≤ 50 s/cycle at + 44–51 eV of Ox+ ion energy) could be identified, and at the ALE conditions, a precise etch rate of ~2.6 Å/cycle was obtained while increasing the W etch depth linearly with increasing the number of etch cycles. At the optimized W ALE conditions, the W surface roughness after the W ALE was similar to the as‐received W and the etch selectivity over SiO2 was close to infinite. However, after the W ALE, ~ 10% F diffused into W was observed on the etched W surface, and which could be removed by a following process.

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“…1 A complementary etching technique has not, until recently, been established. 2 While potential benefits of atomic layer etch processes have been formulated, 3 a clear approach to reaching those benefits had not been identified. Possible pathways have been identified.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of ALE processes for patterning

et al. 2016

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The need for continued device scaling along with the increasing demand for high precision have lead to the development of atomic layer etch processes in semiconductor manufacturing. We have tested this new methodology with regard to patterning applications. While these new plasma-enhanced atomic layer etch (PE-ALE) processes show encouraging results, most patterning applications are best realized by optimizations through discharge chemistry and/or plasma parameters. While PE-ALE approaches seem to have limited success for trilayer patterning applications, significant improvements were obtained when applying them to small pitch. In particular the increased selectivity to OPL seems to offer a potential benefit for patterning high aspect ratio features.

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Atomic Layer Etching: An Industry Perspective

Cited by 134 publications

References 25 publications

Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

Anisotropic atomic layer etching of W using fluorine radicals/oxygen ion beam

Evaluation of ALE processes for patterning

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