Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology

Tsang, P. J.; Ogura, S.; Walker, William W.; Shepard, J.; Critchlow, D.L.

doi:10.1109/jssc.1982.1051720

Cited by 6 publications

(5 citation statements)

References 8 publications

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“…Oxide spacers along gate edges, as employed in lightly doped drain devices (36)(37)(38), can be used to ameliorate the edge degradation effect, as well as reduce gate/drain and gate/source overlap capacitances. Spacers that were only 20 nm wide reduced edge degradation, whereas 75 nm spacers almost totally prevented the degradation (1).…”

Section: ~-Gate Oxide Field Oxidementioning

confidence: 99%

Characterization of Enhanced Perimeter Leakage in MOS Structures Following Ion Implantation

Stinson

Osburn

1990

J. Electrochem. Soc.

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An enhanced leakage current through the gate oxide insulator following ion implantation of source/drain regions in self-aligned gate CMOS devices has been observed with thin gate oxides. A systematic characterization of this phenomena shows that the problem is related to physical damage around the edge of the structure, degrading the integrity of the insulator. Heavier implant atoms like arsenic result in more severely degraded gate structures while the effect of lighter atoms like boron is hardly apparent at normal dose levels. The mechanism for current flow through the structure remains tunneling (as it is normally for current flow through a MOS structure), and is modeled by a reduced tunneling barrier height.MOSFET devices having lithographic features of 0.5 ~m and under require very thin gate oxides and employ ion implantation into patterned gate electrodes to form selfaligned junctions. A low-field breakdown phenomena, through these thin gate oxides, associated with the arsenic source/drain implantation step (1 x 1015-1 x 10 I~ cm -2) for fabricating self-aligned MOSFETs was first reported in 1982 (1). For a 1 x 1016 As/cm 2 dose, at 50 keV, the group found an average breakdown field of 2.2 MV/cm for a 10 nm oxide thickness, whereas unimplanted control samples demonstrated breakdown fields well in excess of 10 MV/cm. The effect was seen in structures which had gate electrode edges directly over thin oxide regions, as is typical for source/drain implants in MOS transistor fabrication as shown in Fig. 1. Capacitor structures with their gate edges overlapping thicker field oxide did not demonstrate low-field breakdown. It was reported that the degradation of MOS dielectric breakdown was most severe in the thinnest gate oxides examined for the highest dose implants. This edge breakdown effect was subsequently described in several other publications (2-6). Flowers had found a similar effect for several other common doping methods besides ion implantation (2). He found that degradation occurred in MOS structures following POCla polysilicon doping, spin on doping techniques, as well as ion implantation. Phosphorus implantation was also demonstrated to degrade the oxide dielectric strength which was attributed to barrier lowering due to very high dopant concentrations residing within the gate oxide at the perimeter just under the gate (3). The Varian group (5) had reported charging during implantation was at least partially responsible for gate oxide degradation. This present study was undertaken to provide a systematic characterization of the oxide degradation in order to ultimately provide a satisfactory explanation of the phenomena.It could be postulated that many factors acting either independently or synergistically, are important in causing this edge breakdown effect. For example, these mechanisms may include; gate charging, radiation damage, recoiled atoms, and ion mixing at the gate edge. Over the years, the effect of ion implantation into or through gate oxides has been documented in many studies. Few studi...

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Section: ~-Gate Oxide Field Oxidementioning

confidence: 99%

Characterization of Enhanced Perimeter Leakage in MOS Structures Following Ion Implantation

Stinson

Osburn

1990

J. Electrochem. Soc.

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“…Careful drain engineering has been done to reduce Recently, a lightly doped drain (LDD) structure, which uses a lightly doped buffer zone between the n + drain and the gate, has been proposed [31]. The Em in Eq.…”

Section: Lightly Doped Drain Solutionmentioning

confidence: 99%

“…Device structures and associated lateral Ε-fields for conventional and lightly doped drain (LOO) η-channel FET[31].…”

mentioning

confidence: 99%

CMOS — The emerging VLSI technology

Chen

1986

IEEE Circuits Devices Mag.

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This paper reviews the recent evolution in CMOS as the emerging very-large-scale-integrated (VLSI) technology. Various CMOS tech nologies and their impact on circuit performance and reliability are dis cussed and compared in generic and special circuit applications. Key issues in CMOS scaling, such as hot-electron effects, buried-channel character istics, latch-up, and isolation requirements, are briefly described. State-ofthe-art CMOS design rules are also addressed. The paper concludes with a discussion on the future trends of CMOS technology development in VLSI circuits.

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“…The process is also applicable to smaller devices. The process sequence for short-channel transistors is normally altered to provide for a graded drain [ 3 ] , [4] rather than to use the heavy arsenic implant prior to sidewall oxide shown in Table I. It has been confirmed that submicrometer spaces can be silicided and that suitable submicrometer devices can be fabricated.…”

Section: Device Fabricationmentioning

confidence: 99%

Fabrication of Mo-gate/Ti—silicide-clad-moat MOS Devices by use of multilayer-glass depositions

McDavid

1984

IEEE Electron Device Lett.

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Abshakt-A novel technique is described which uses undoped and doped glass depositions at the gate level to make a molybdenum-metal-gate process compatible with a direct-react titanium-silicide clad-moat process. The method is applicable to submeter micro design-rule MQS IC devices and yields 0.3 Q / O and 2.0 Q / c I for gate and moat levels, respectively. I. INTRODUCTIONEQUIREMEWTS for future MOS VLSI devices include low-resistance replacements for the doped-polysilicon or silicide-clad-polysilicon gate material and for the diffused source/drain areas. Sheet resistances on the order of 0.3 CliU for the gate and 3 CliU for sourceidrain regions are needed for speed improvement and for design flexibility for a broad range of VLSI memory and logic devices.A simultaneous direct-react silicide-cladding of moat and gate levels has been described[l] which can be used to provide sheet resistances for both levels of about 1. CliC [2]and such a process is expected to be applicable to many devices. It is the purpose here, however, to describe a new process which further reduces the gate sheet-resistance, a critical parameter for access times, by a factor of four, by the use of a refractory metal gate rather than a titanium-silicideipolysilicon sandwich structure. The essential feature of this new process is that it provides compatibility between the use of a refractory metal gate and a direct react cladding of the moat level by employing a multilayer-glass-encapsulation of the metal gate.

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Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology

Cited by 6 publications

References 8 publications

Characterization of Enhanced Perimeter Leakage in MOS Structures Following Ion Implantation

Characterization of Enhanced Perimeter Leakage in MOS Structures Following Ion Implantation

CMOS — The emerging VLSI technology

Fabrication of Mo-gate/Ti—silicide-clad-moat MOS Devices by use of multilayer-glass depositions

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