CMOS — The emerging VLSI technology

Chen, J. V.

doi:10.1109/mcd.1986.6311801

Cited by 36 publications

(4 citation statements)

References 39 publications

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“…10, could also be fabricated along these lines. Another interesting aspect of CMOS polysilicon is its capability to form resistive elements (6). The layout designer can form polysilicon layers with four different resistivities.just by selecting suitable ion implantation mask layers.…”

Section: Discussionmentioning

confidence: 99%

“…3a. In this section, layout terminologies are used to identify various CMOS layers (6). Here, two device wells are defined with a polysilicon strip placed over them.…”

Section: Poly Microbridge Design In Standard Complementarymentioning

confidence: 99%

“…However, ion-implanted polysilicon is not desirable for the fabrication of microbridges because of its weak mechanical strength, and a polysilicon layer without ion implantation is required. Consequently, the portion of the die where the microbridge is to be located is masked from any ion implantation by the proper use of P+ and N' mask layers (6). This step is achieved by an unconventional layout design specific to the fabrication of microbridges in standard CMOS technology.…”

Section: Poly Microbridge Design In Standard Complementarymentioning

confidence: 99%

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Fabrication of microbridges in standard complementary metal oxide semiconductor technology

Parameswaran¹,

Ristic²,

Dhaded³

et al. 1989

Can. J. Phys.

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Complementary metal oxide semiconductor (CMOS) technology is one of the leading fabrication technologies of the semiconductor integrated-circuit industry. We have discovered features inherent in the standard CMOS fabrication process that lend themselves to the manufacturing of micromechanical structures for sensor applications. In this paper we present an unconventional layout design methodology that allows us to exploit the standard CMOS process for producing microbridges. Two types of rnicrobridges, bare polysilicon microbridges and sandwiched oxide rnicrobridges, have been manufactured by first irnplernenting a special layout design in an industrial digital CMOS process, followed by a postprocessing etching step.Le procCdC semi-conducteur i oxyde de rnttal cornplkrnentaire (CMOS) est I'une des principales technologies de fabrication de l'industrie des circuits semiconducteurs intkgrks. Nous avons dkcouvert des caractCristiques inhCrentes au procCdC de fabrication CMOS qui se prctent bien i la production de structures rnicrornkcaniques pour utilisation dans des senseurs. Dans cet article, nous presentons une mCthodologie non conventionnelle qui permet d'adapter le procCdC CMOS standard B la production de rnicroponts. Deux types de rnicroponts, en polysilicium seulernent ou avec oxyde en sandwich, ont Ctk fabriquCs, en rnettant d'abord en oeuvre cette nouvelle rnCthodologie et en passant ensuite i I'ktape de la lithographie. [Traduit par la revue]Can. 1. Phys. 67, 184 (1989) IntroductionSilicon micromachining technology is capable of producing a variety of mechanical microstructures for sensor and actuator applications (1). The fabrication of microbridges, cantilever beams, microvalves, and even pin joints and gears is a reality today (2, 3). These microstructures enable relatively accurate measurements of force, vibration, acceleration, displacement, and vapor concentration. Despite the overwhelming potential for applications associated with these microstructures, only a few commercial sensors are fabricated using this technology. The main reason for this limitation is the technological incompatibility between the existing silicon micromachining technology and the commercial integrated-circuit (IC) fabrication technology (4). However, it is highly desirable to have the sensor with-the signal-conditioning circuitry on the same chip, because it results in a high signal-to-noise ratio for transmitting a reliable transduced signal to a control system or display (5).To investigate and possibly offer a solution to this problem, we propose a new methodology to fabricate micromechanical structures for sensor applications. Our method is based on a standard industrial complementary metal oxide semiconductor (CMOS) process, optimized for high yield, component density, and reliability. To realize micromechanical structures in a standard CMOS process, we employ an unconventional layout design methodology to obtain a basic structure. A postprocessing step, an isotropic or an anisotropic etching, is then used to release free...

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Section: Discussionmentioning

confidence: 99%

“…3a. In this section, layout terminologies are used to identify various CMOS layers (6). Here, two device wells are defined with a polysilicon strip placed over them.…”

Section: Poly Microbridge Design In Standard Complementarymentioning

confidence: 99%

Section: Poly Microbridge Design In Standard Complementarymentioning

confidence: 99%

See 1 more Smart Citation

Fabrication of microbridges in standard complementary metal oxide semiconductor technology

Parameswaran¹,

Ristic²,

Dhaded³

et al. 1989

Can. J. Phys.

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“…The merit of a particular technology is usually judged by its gate delay, power consumption, noise immunity and logic capacity. A comparison of various technologies can be found in [SoI82], while the reasons for the dominance of CMOS as today's chosen technology are explained in [Che86,Sh088]. Implementation style choices include programmable logic devices, gate arrays, standard cells, and module generators.…”

Section: 2 a Decision-making Perspective Versus A Transformation Permentioning

confidence: 99%

ASIC System Design with VHDL: A Paradigm

Leung¹,

Shanblatt²

1989

The Kluwer International Series in Engineering and Computer Science

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Logic Minimization Algorithms jor VLSI Synthesis. R.K. Brayton, 0.0. Hachtel, C.T. McMullen, and A.L. Sangiovanni-Vincentelli. ISBN 0-89838-164-9. Adaptive Filters: Structures, Algorithms, and Applications. M.L. Honig and D.O. Messerschmitt. ISBN 0-89838-163-0. Introduction to VLSI Silicon Devices: Physics, Technology and Characterization. B. El-Kareh and R.I. Bombard. ISBN 0-89838-210-6. Latchup in CMOS Technology: The Problem and Its Cure. R.R. Troutman. ISBN 0-89838-215-7. Digital CMOS Circuit Design. M. Annaratone. ISBN 0-89838-224-6. The Bounding Approach to VLSI Circuit Simulation. C.A. Zukowski. ISBN 0-89838-176-2. Multi-Level Simulationjor VLSI Design. D.O. Hill and D.R. Coelho. ISBN 0-89838-184-3. RelQXlltion Techniques jor the Simulation oj VLSI Circuits. 1. White and A. Sangiovanni-Vincentelli. ISBN 0-89838-186-X. VLSI CAD Tools and Applications. W. Fichtner and M. Morf, editors. ISBN 0-89838-193-2. A VLSI Architecturejor Concurrent Data Structures. W.l. Dally. ISBN 0-89838-235-1. Yield Simulation jor Integrated Circuits. D.M.H. Walker. ISBN 0-89838-244-0.

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