Fabrication and properties of ultrasmall Si wire arrays with circuits by vapor–liquid–solid growth

Kawano, Takeshi; Kato, Yoshiko; Futagawa, Masato; Takao, Hidekuni; Sawada, Kazuaki; Ishida, M.

doi:10.1016/s0924-4247(02)00008-0

Cited by 54 publications

(41 citation statements)

References 7 publications

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“…5 Control of the size and position of VLS-grown wires has been demonstrated, 6,7 particularly in the case of Si by patterning of a surface oxide. [8][9][10] Wire array growth, however, has only been achieved over relatively small areas, unless a template is used. 11 We demonstrate herein the VLS growth of arrays of Si wires having diameters of 1.5 m and lengths of Ͼ70 m, with very low defect densities, over areas Ͼ1 cm 2 , without the use of a template.…”

mentioning

confidence: 99%

Growth of vertically aligned Si wire arrays over large areas (>1cm2) with Au and Cu catalysts

Kayes

Filler

Putnam

et al. 2007

Applied Physics Letters

285

273

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Arrays of vertically oriented Si wires with diameters of 1.5 m and lengths of up to 75 m were grown over areas Ͼ1 cm 2 by photolithographically patterning an oxide buffer layer, followed by vapor-liquid-solid growth with either Au or Cu as the growth catalyst. The pattern fidelity depended critically on the presence of the oxide layer, which prevented migration of the catalyst on the surface during annealing and in the early stages of wire growth. These arrays can be used as the absorber material in novel photovoltaic architectures and potentially in photonic crystals in which large areas are needed. © 2007 American Institute of Physics. ͓DOI: 10.1063/1.2779236͔Photovoltaic devices designed to achieve high cell efficiency with low-quality materials must have optically thick absorber layers, yet must simultaneously allow efficient collection of low diffusion length charge carriers. An attractive approach involves an array of vertically aligned semiconducting wires to enable carrier collection in the wires' radial direction, a distance that is short relative to their optical thickness ͑i.e. length͒.1 Well-defined wire arrays have been produced using lithographic patterning followed by anisotropic etching, 2,3 but such methods require large areas of high-quality substrate materials. In contrast, wires of various materials 4 have also been grown 'bottom up' by the vaporliquid-solid ͑VLS͒ process.5 Control of the size and position of VLS-grown wires has been demonstrated, 6,7 particularly in the case of Si by patterning of a surface oxide.8-10 Wire array growth, however, has only been achieved over relatively small areas, unless a template is used.11 We demonstrate herein the VLS growth of arrays of Si wires having diameters of 1.5 m and lengths of Ͼ70 m, with very low defect densities, over areas Ͼ1 cm 2 , without the use of a template.Attempts to grow Si wire arrays did not yield high pattern fidelity when the catalyst was not confined. Wires were grown by photolithographically patterning S1813 photoresist ͑Microchem͒ on a clean Si͑111͒ wafer, then exposing it for 5 s to buffered HF͑aqueous͒ ͑Transene, Inc., 9% HF, 32% NH 4 F͒, followed by evaporation of 500 nm of Au and lift-off of the resist. This produced a square array of 3 m diameter Au islands with a center-to-center pitch of 7 m. Samples were then annealed in a tube furnace at 900-1000°C for 20 min under 1 atm of H 2 at a flow rate of 1000 SCCM ͑SCCM denotes cubic centimeters per minute at STP͒, followed by wire growth under 1 atm of H 2 and SiCl 4 , at flow rates of 1000 and 20 SCCM, respectively. This produced arrays of low fidelity, with no control over the wire diameter or wire position ͑not shown͒. Examination of the samples after a 20 min H 2 anneal only revealed that this behavior was due to substantial agglomeration of the catalyst ͑Fig. 1͒.The successful production of large-area Si wire arrays involved the use of an oxide buffer layer to confine the VLS catalyst to the desired areas in the pattern. To implement this approach, a 300 nm oxide was ther...

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mentioning

confidence: 99%

Growth of vertically aligned Si wire arrays over large areas (>1cm2) with Au and Cu catalysts

Kayes

Filler

Putnam

et al. 2007

Applied Physics Letters

285

273

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“…The high-density and low-invasive silicon (Si) probe with a few microns in diameter was fabricated using selective vapor-liquid-solid (VLS) growth method on Si (111) wafer in predetermined positions and probe sizes [27]. The diameter of the Si probes is controlled using patterned gold dots deposition while the probe length is controlled applying the growth rate of 0.5 µm/min.…”

Section: Silicon-wire Arraymentioning

confidence: 99%

“…The greatest advantage of this fabrication technology is that the microelectrode array can be integrated with IC signal processors on the same substrate The VLS growth was performed at 700 ºC for 2 h. Reprinted with permission from Ref. [27].…”

Section: Silicon-wire Arraymentioning

confidence: 99%

High-density 3D pyramid-shaped microelectrode arrays for brain-machine interface applications

Motlagh

2014

2014 IEEE Biomedical Circuits and Systems Conference (BioCAS) Proceedings

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“…Refs. [1][2][3] show that probe-like Si single crystal can be grown in /1 1 1S direction on Si(1 1 1) substrate by a special type growth mechanism of Si, the name of which is vaporliquid-solid (VLS) growth method. This method begins with the formation of dots of a metallic catalyst (normally Au) on Si substrate.…”

Section: Introductionmentioning

confidence: 99%

“…As long as the supply of Si precursor remains available, the precipitation of Si atoms continues and thus results in the growth of a probe-like Si crystal perpendicular to the Si surface. From the previous reports, we find that the study of VLS-grown Si microprobes and some applications of these microprobes have been presented [3][4][5]. For example, some researchers [4] applied VLS-grown Si probes as the pins for developing high-resolution probe-card for integrated circuit (IC) testing and some others [5] investigated the feasibility of using Si microprobe for neural activity recording.…”

Section: Introductionmentioning

confidence: 99%

High-yield growth of p-Si microprobe arrays by selective vapor–liquid–solid method using in situ doping and their properties

Islam

Kawashima

Sawada

et al. 2007

Journal of Crystal Growth

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Fabrication and properties of ultrasmall Si wire arrays with circuits by vapor–liquid–solid growth

Cited by 54 publications

References 7 publications

Growth of vertically aligned Si wire arrays over large areas (>1cm2) with Au and Cu catalysts

Growth of vertically aligned Si wire arrays over large areas (>1cm2) with Au and Cu catalysts

High-density 3D pyramid-shaped microelectrode arrays for brain-machine interface applications

High-yield growth of p-Si microprobe arrays by selective vapor–liquid–solid method using in situ doping and their properties

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Fabrication and properties of ultrasmall Si wire arrays with circuits by vapor–liquid–solid growth

Cited by 54 publications

References 7 publications

Growth of vertically aligned Si wire arrays over large areas (&gt;1cm2) with Au and Cu catalysts

Growth of vertically aligned Si wire arrays over large areas (&gt;1cm2) with Au and Cu catalysts

High-density 3D pyramid-shaped microelectrode arrays for brain-machine interface applications

High-yield growth of p-Si microprobe arrays by selective vapor–liquid–solid method using in situ doping and their properties

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Growth of vertically aligned Si wire arrays over large areas (>1cm2) with Au and Cu catalysts

Growth of vertically aligned Si wire arrays over large areas (>1cm2) with Au and Cu catalysts