Fabrication and characterization of metal-to-metal interconnect structures for 3-D integration

Abstract

The use of collapsible (solder) bump interconnects in pixel detector hybridization has been shown to be very successful. However, as pixel sizes decrease, the use of non-collapsible metal-to-metal bump bonding methods is needed to push the interconnect dimensions smaller. Furthermore, these interconnects are compatible with 3D intgration technologies which are being considered to increase overall pixel and system performance. These metal-to-metal bonding structures provide robust mechanical and electrical connections and allow for a dramatic increase in pixel density. Of particular interest are Cu-Cu thermocompression bonding and Cu/Sn-Cu solid-liquid diffusion bonding processes. Working with Fermilab, RTI undertook a demonstration to show that these bump structures could be reliably used to interconnect devices designed with 20 micron I/O pitch. Cu and Cu/Sn bump fabrication processes were developed to provide a well-controlled surface topography necessary for the formation of low resistance, high yielding, and reliable interconnects. The electrical resistance and yield has been quantified based on electrical measurements of daisy chain test structures and the mechanical strength of the bonding has been quantified through die shear testing. The reliability has been characterized through studies of the impact of thermal exposure on the mechanical performance of the bonds. Cross-section SEM analysis, coupled with high resolution energy dispersive spectroscopy, has provided insight into the physical and chemical nature of the bonding interfaces and aided in the evaluation of the long-term stability of the bonds.

High density Cu-Cu interconnect bonding for 3-D integration

“…Cu-Cu bonding may also be preferred for ICs with Cu top metal structures because less back-end-of-line processing is required for the Cu terminated ICs. Regardless of the IC top metal material, Cu-Cu bonding requires less pre-bond preparation of the Cu bond pads/bumps (i.e., no flux or plasma pre-treatment) than that required for Cu/Sn bumps in Cu/Sn-Cu bonding [6].…”

10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack

“…However, undercut phenomenon, which is occurred during wet etching process, is big issue to achieve small size and fine pitch micro-bumps. Recently, several activities have reported to apply dry etching process for removing seed and barrier layers [4][5]. However, they have still large bump pitch and not CMOS compatible processes.…”

“…However, more than 4.3 mN/bump bonding force, all bumps are successfully connected as shown in Table II. However minimum bonding force for stable bonding is lower than that for electroplated Cu/Sn bumps [4]. We evaluate the impact of bonding temperature on the micro-joining characteristics of Cu/Sn micro-bumps.…”

Optimized ultra-thin manganin alloy passivated fine-pitch damascene compatible bump-less Cu–Cu bonding at sub 200 °C for three-dimensional Integration applications

“…[1][2][3] A plausible option for 3D stacking is Cu-Cu wafer bonding as Cu has good electrical conductivity and is CMOS compatible. [4][5][6] Surface passivation is an essential step for low temperature Cu-Cu wafer bonding because copper is highly reactive to ambient oxygen as oxidized copper acts as a barrier for interdiffusion of Cu across the interface. It necessitates higher temperature and=or pressure for achieving a good quality bonding.…”

“…Also, many researchers proposed techniques for the removal of native oxide from Cu surface by pre-bond cleaning step using wet chemistry. Employed chemistry for pre-bond wet cleaning include but not limited to acetic acid, 14,15) citric acid, 16) sulfuric acid, 17) hydrochloric acid 18,19) treatments and combinations thereof. However, prolonged immersion of the acids may degrade the performance of underneath active devices.…”