Extremely Low Keff (1.9) Cu Interconnects with Air Gap Formed Using SiOC

Abstract

Dual damascene Cu interconnects with Keff below 2.0 have been demonstrated for the first time. Air gaps between Cu lines were formed with a low K SiOC film in a carefully designed manner. CoWP cap layers were introduced to protect the Cu lines and to eliminate a dielectric liner layer. In addition, AGE (Air Gap Exclusion) was applied to solve crucial problems related to the air gaps. Keff of 1.9 was obtained at 65nm design rule, which surpassed by far ITRS target (2.5 2.8) for hp45. It was also confirmed that leakage current between lines was suppressed by the formation of the air gaps.

Low–Dielectric Constant Insulators for Future Integrated Circuits and Packages

“…In one example, an additional lithography step was used to etch holes in SiCOH between copper lines (105,106). After the etch step, deposition of SiCOH was performed to deposit more material on the surface of the structure but not in the trench; this process pinches off the top portion of the dielectric layer.…”

Timing Criticality-Aware Design Optimization Using BEOL Air Gap Technology on Consecutive Metal Layers

“…The practical use of the AG requires a definition of the key design rules to avoid process risks. First, the AG is allowed only at the minimum spacing [11,12]. Because of the self-aligned AG process, the IMD recess width for the AG increases with the spacing width.…”

“…Then, the pinch-off point to close the AG becomes higher, resulting in the risk of contact with the trench bottom of the upper metal level. Second, the AG is prohibited beside the upper via [11][12][13][14]. If a part of the via bottom is outside of the metal line because of size and overlay variation, the via hole is connected to the AG cavity.…”

“…The ultimate solution for a low k-value is the exclusion of all materials from the IMD, which is called an air gap (AG). There are two types of AG processes: (1) removal of the sacrificial material via thermal decomposition or chemical treatment [6][7][8][9][10] through the upper dielectric layer and (2) etching back the IMD followed by pinch-off of the next IMD deposition [11][12][13][14][15]. In the latter case, the AG can be formed selectively at the critical path, leaving dielectric materials in other places, which can retain the mechanical strength.…”

Dielectric failure mechanisms in advanced Cu/low-k interconnect architecture

“…In order to keep pace with the gate scaling beyond the 90 nm technology node, second xerogel [15], which are basically porous silica-based dielectrics. Ultimately, to achieve the most idealistic interconnect system with the lowest intra-line capacitance is by introducing air gaps as the IMD dielectric [16,17].…”