Extraction of electrical parameters of floating gate devices for circuit analysis, simulation, and design

Mondragon-Torres, Antonio F.; Schneider, M.C.; Sánchez-Sinencio, E.

doi:10.1109/mwscas.2002.1187219

Cited by 12 publications

(15 citation statements)

References 5 publications

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“…The drain-gate voltage at the diode connected MI-FGMOS transistor becomes (19) Equation (19) is in the form required by (17), and it is also in the form of the general expression of the algorithm (10). This validates that the proposed implementation yields an algorithm that can be mapped directly into a transistor level implementation.…”

Section: B Siso Analog Circuit Implementationsupporting

confidence: 52%

“…This allow us to include a capacitance between the FG and the n well. Also, we are able to model the intrinsic charge stored in the FG capacitor [19]. This charge can be trapped during the fabrication process, or can be externally programmed by the user.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…A set of technology-dependent parameter values in (16) have to be determined. A complete methodology for the extraction of electrical parameters for FG transistors is given in [19].…”

Section: A Mi-fgmos As Processing Elementsmentioning

confidence: 99%

See 2 more Smart Citations

Floating-gate analog implementation of the additive soft-input soft-output decoding algorithm

Mondragon-Torres

Sánchez-Sinencio²,

Narayanan³

2003

IEEE Trans. Circuits Syst. I

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The soft-input soft-output algorithm is used to iteratively decode concatenated codes. To efficiently implement this algorithm, an additive form in the logarithmic domain is employed. A novel analog implementation using CMOS translinear circuits is proposed. A multiple-input floating-gate CMOS transistor working in the subthreshold region is used as the main translinear computing element. The proposed approach allows a direct mapping between the decoding algorithm and the circuit implementation. Experimental CMOS chip results are in good agreement with theoretical and simulation results.

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Section: B Siso Analog Circuit Implementationsupporting

confidence: 52%

Section: Simulation Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Floating-gate analog implementation of the additive soft-input soft-output decoding algorithm

Mondragon-Torres

Sánchez-Sinencio²,

Narayanan³

2003

IEEE Trans. Circuits Syst. I

Self Cite

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“…MIFG-MOS transistor was modelled as described in [6] with a capacitors of 2 pF. Figure 4 plots the variation of the output current according to the differential input voltage for various values of the parameter A.…”

Section: Simulations Resultsmentioning

confidence: 99%

An alternative to source degeneration of CMOS differential pair

Mourabit

Pittet

2009

Analog Integr Circ Sig Process

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This paper presents a method to extend linear range of conventional CMOS source-coupled pair with transistor polarised on saturation of strong inversion. The used principle is similar to the principle of source degeneration, but the additional device is horizontally added, in parallel with the input transistors, which overcame the constraints on common mode range and supply voltage and allow low voltage operation. SPICE simulations using 0.35 lm CMOS process and a bias current of 10 lA, show that for less than 1% of transconductance variation, the linear range is up to 0.35 V pp in comparison to 0.1 V pp for source-degenerated pair, and 0.01 V pp for conventional differential pair, under the same biasing current and geometrical dimensions.

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“…There are some structures that have become popular within the analog de-signer community. The most popular modeling structures are a "coupling" model developed by Mondragon-Torres et al [7] and a synapse model shown by Rahimi et al [8] and Gray et al [9]. The coupling model in [10] focuses mainly on modeling how the parasitic capacitances effect the operational characteristics of the device.…”

Section: Previous Modeling Attemptsmentioning

confidence: 99%

A Comprehensive Simulation Model for Floating Gate Transistors

Rapp¹

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Floating-gate transistors have proven to be extremely useful devices in the development of analog systems; however, the inability to properly simulate these devices has held back their adoption. The objective of this work was to develop a complete simulation model for a floating-gate (FG) MOSFET using both standard SPICE primitives and also MOSFET models taken directly from foundry characterizations. This new simulation model will give analog designers the ability simulate all aspects of floating-gate device operation including transient, AC and DC characteristics. This work describes the development of this model and demonstrates its use in various applications.

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Extraction of electrical parameters of floating gate devices for circuit analysis, simulation, and design

Cited by 12 publications

References 5 publications

Floating-gate analog implementation of the additive soft-input soft-output decoding algorithm

Floating-gate analog implementation of the additive soft-input soft-output decoding algorithm

An alternative to source degeneration of CMOS differential pair

A Comprehensive Simulation Model for Floating Gate Transistors

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