Floating-gate analog implementation of the additive soft-input soft-output decoding algorithm

Abstract

The soft-input soft-output algorithm is used to iteratively decode concatenated codes. To efficiently implement this algorithm, an additive form in the logarithmic domain is employed. A novel analog implementation using CMOS translinear circuits is proposed. A multiple-input floating-gate CMOS transistor working in the subthreshold region is used as the main translinear computing element. The proposed approach allows a direct mapping between the decoding algorithm and the circuit implementation. Experimental CMOS chip results are in good agreement with theoretical and simulation results.

Iterative decoding in analog VLSI

“…We also noted that none of the previously reported analog iterative decoders use favorable standard CMOS technology in the strong inversion biasing condition. Either they use non-standard technologies such as BiCMOS technology [19]- [24] or they use favorable CMOS technology but not in strong inversion biasing condition [25]- [29].…”

“…For each signal to noise ratio at least 200 wrong codewords have been observed at the output of the decoder with the ex ception of 7dB for the case with fixed number of iterations. For this simulation point only 25 wrong codewords have been observed after running the simulations for a long period o f time. This is because the average number of iterations at this signal to noise ratio is about 1.38 and fixing the iteration number at 50.000 significantly increases the simulation time.…”

“…In [25], the authors have implemented one stage of the alpha metric computation of Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm for an 8 -state convolutional code. In [20], [26], and [29] implementation of turbo decoders with interleaver lengths 16, 16, and 40 have been respectively reported.…”

“…To handle these problems for large analog decoders in [79] hardware sharing was proposed. Soon, it was found that by using subthreshold (weak inversion biasing) CMOS Gilbert multipliers it is possible to implement belief propaga tion with CMOS circuits [15], [25]- [29], [85]. A CMOS design is more favorable because it is more affordable and consumes less area.…”

Αρχιτεκτονικές Και Υλοποίηση Κωδίκων Διόρθωσης Λαθών

“…Εντούτοις, η υλοποίηση αναλογικών αποκωδικοποιητών χρησιμοποιώντας τις προαναφερθείσες αρχιτεκτονικές δεν έχει πραγματοποιηθεί έως τώρα. O Mondragon στα πλαίσια της διδακτορικής του διατριβής στο πανεπιστήμιο Texas A&M πρότεινε ένα κύκλωμα sum-product βασιζόμενο στην διάταξη floating-gate MOS [50,51]. Τα κυκλώματα αυτά σχετίζονται πάρα πολύ με τα κυκλώματα floating-gate MOS, τα οποία χρησιμοποιούνται σε νευρομορφικά συστήματα [52].…”