Extension of practical k1 limit in EUV lithography

Park, Sarohan; Lee, Inwhan; Koo, Sunyoung; Lee, Junghyung; Lim, Chang-Moon

doi:10.1117/12.2219546

Cited by 2 publications

(2 citation statements)

References 1 publication

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“…EUV lithography has been used in chip mass production since 2019, when TSMC announced at the IEDM that EUV technology satisfied high volume production requirements; thus, they started the volume ramp of the enhanced 7 nm technology with EUV insertion [152]. In the same year, the first few consumer chips at 7 nm nodes with reference to EUV processing lithography, HUAWEI Kirin 990 Series 5G SoC (Shenzhen, China) [8,153], and Samsung Exynos 9825 (Suwon, Republic of Korea) [152], were also announced. EUV has been used in mass production at DRAM since Samsung's announcement of the 1z process node [154].…”

Section: Euv In Mass Productionmentioning

confidence: 99%

“…Since the successful EUV adoption in mass production [152,153,156], this has brought the k1 factor back to the low-contrast (k1 > 0.25) region from the no-contrast (k1 < 0.25) region, as shown in Figure 13. From 22 nm to 7 nm, there is no contrast and no imaging using single lithographic exposure, thus LELE and SAmP are used for pitch division.…”

Section: Euv In Mass Productionmentioning

confidence: 99%

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CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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Section: Euv In Mass Productionmentioning

confidence: 99%

Section: Euv In Mass Productionmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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Stochastics in extreme ultraviolet lithography: investigating the role of microscopic resist properties for metal-oxide-based resists

Maas

Lare

Rispens

et al. 2018

J. Micro/Nanolith. MEMS MOEMS

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Due to the high energy of extreme ultraviolet (EUV) photons, stochastic effects become more important at a constant dose when compared with deep ultraviolet exposures. Photoresists are used to transfer information from the aerial image into physical features and play an important role in the transduction of these stochastic effects. Recently, metal-oxide-based nonchemically amplified resists (non-CARs) have attracted a lot of attention. We study how the properties of these non-CARs impact the local critical dimension uniformity (LCDU) of a regular contact hole array printed with EUV lithography using Monte Carlo simulations and an analytical model. We benchmark both the simulations and the analytical model to experimental data, and then use the flexibility of both methods to systematically investigate the role of microscopic resist properties in the final LCDU. It is found that metal-oxide clusters should be <1 nm in diameter, otherwise granularity will have a significant contribution to LCDU. When varying resist properties to change the resist dose-to-size, we find that the LCDU scaling with dose depends on how the resist is modified. After performing an overall sensitivity analysis to identify the optimum scaling of LCDU with dose, we find a scaling of dose −0.5 when the development threshold is modified, and a scaling of dose −0.33 when core radius or the quantum efficiency is changed.

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Extension of practical k1 limit in EUV lithography

Cited by 2 publications

References 1 publication

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Stochastics in extreme ultraviolet lithography: investigating the role of microscopic resist properties for metal-oxide-based resists

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