Extendibility Study of a PVD Cu Seed Process with Ar+ Rf-Plasma Enhanced Coverage for 45nm Interconnects

Abstract

We present the results of a systematic benchmarking study, using 45nm-groundrule structures, of a commercially-available ionized PVD Cu technology which employs an in-situ Ar+ radio-frequency (Rf) plasma capability for enhanced coverage, and compare its performance and extendibility against the same seedlayer process operated in conventional low-pressure mode. Studies of single-damascene lines and dual-damascene via structures indicate that the PVD Cu seedlayer with Rf-Plasma enhancement enables a reduction of the PVD Cu seed thickness on the order of 35%, based on studies of Cu voiding, via-yield degradation, and transmission-electron microscopy (TEM). These results illustrate the critical importance of the Rf-plasma resputter capability in extending the PVD Cu process to advanced groundrules at 45nm and beyond.

Copper Metal for Semiconductor Interconnects

“…However, the accompanied problems are poor step coverage and Cu diffusion into the dielectric. The improved Noble and Precious Metals -Properties, Nanoscale Effects and Applications sputtering method or atomic layer deposition method can be used to deposit a thinner liner layer [44][45][46]. The most promising method is to adopt a self-forming barrier process by depositing Mnbased film.…”

Process Technology for Copper Interconnects

“…In principle, increasing the grain size of Cu in narrow lines would be very beneficial. Thinner liners are possible by using improved sputtering methods [80][81][82], atomic layer deposition instead of sputter deposition [99], or by using self-forming barrier layers such as Mn silicate [100]. A more promising approach is to reduce the thickness of the refractory metal liner (Figure 8.15).…”

Electrodeposited Cu Film Morphology on Thin PVD Cu Seed Layers

“…Physical vapor deposited (PVD) Cu seed may become discontinuous in narrow features and not allow for good initiation of plated Cu, resulting in a seam or void at the barrier/Cu interface that can degrade reliability performance (1). Over the last several years, a number of significant PVD processing improvements have helped extend this approach (along with the subsequent electroplated Cu fill step) to smaller dimensions (2)(3)(4)(5). Despite these advances, metallization of tight interconnect feature geometries required for future CMOS technologies will certainly further challenge the extension of this approach.…”