Extendibility of NiPt Silicide Contacts for CMOS Technology Demonstrated to the 22-nm Node

Ohuchi, K.; Lavoie, C.; Murray, Conal E.; D'Emic, C.; Chu, J. O.; Yang, Bin; Besser, Paul R.; Gignac, Lynne; Bruley, J.; Singco, G.; Pagette, F.; Topol, Anna W.; Rooks, M. J.; Bucchignano, J.; Narayanan, V.; Khare, Mukesh; Takayanagi, Motowo; Ishimaru, K.; Park, Dae-Gyu; Shahidi, G.; Solomon, P. M.

doi:10.1109/iedm.2007.4418888

Cited by 25 publications

(20 citation statements)

References 3 publications

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“…One of the critical issues is the control of the homogeneity and roughness of the silicide. 8 Another important issue regarding contact materials is their thermal stability that is directly related to the texture or microstructure of the thin films. The important role of nucleation in CoSi 2 formation, however, results in rough silicide/silicon interfaces and nonuniform thin films.…”

Section: Introductionmentioning

confidence: 99%

Nucleation and diffusion during growth of ternary Co1−xNixSi2 thin films studied by complementary techniques in real time

Smeets

Demeulemeester

Keyser

et al. 2008

Journal of Applied Physics

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Simultaneous real-time x-ray diffraction spectroscopy, Rutherford backscattering spectrometry, and sheet resistance measurements to study thin film growth kinetics by Kissinger plots J. Appl. Phys. Nanostructure and giant Hall effect in TM x ( Si O 2 ) 1 − x ( TM = Co , Fe , Ni ) granular system J. Appl. Phys. 99, 08C511 (2006); 10.1063/1.2171013 High-temperature degradation of NiSi films: Agglomeration versus Ni Si 2 nucleation J. Appl. Phys. 98, 033526 (2005); 10.1063/1.2005380 High-resolution investigation of atomic interdiffusion during Co/Ni/Si phase transitionThe growth kinetics of ternary Co 1−x Ni x Si 2 thin films was studied in real time. The "Kissinger" method was applied to the results of ramped sheet resistance measurements to extract the apparent activation energy for the growth process. By simultaneously acquiring sheet resistance, x-ray diffraction and laser light scattering data on one hand and combining resistance measurements and Rutherford backscattering spectrometry on the other hand, we could distinguish between the initial, nucleation controlled thin film growth, and the subsequent diffusion controlled growth. The apparent activation energy for the initial growth decreases with increasing Ni concentration as a result of a lower nucleation barrier for the ternary disilicide. The markedly different microstructure of the ternary Co 1−x Ni x Si 2 films with respect to pure CoSi 2 layers lies at the origin of a lower activation energy for the diffusion controlled growth of the ternary films. Despite the low activation energy, these films grow at a much slower rate than CoSi 2 films due to the large grain size and consequently lower density of grain boundary diffusion paths. These results explain the unexpected high thermal budget required for the formation of low resistivity Co 1−x Ni x Si 2 thin films.

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Section: Introductionmentioning

confidence: 99%

Nucleation and diffusion during growth of ternary Co1−xNixSi2 thin films studied by complementary techniques in real time

Smeets

Demeulemeester

Keyser

et al. 2008

Journal of Applied Physics

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“…In this work, uniform distributed contact resistance model are fitted to match device onresistance at the same overdrive gate voltage for characterizing contact sizing effect of 1x and 2x pitches. The calibrated specific contact resistivity of 3.6x10 -8 :cm 2 is resulted from the distributed contact resistance model which is found to be close to the recent measurement range from IBM alliance research group [7]. The corresponding attached lumped resistance is extracted at 70 :Pm from lumped resistive contact modeling for 1xpitch device case, which shows the limitation of the model for pitch dependence prediction in Fig 5(b).…”

Section: Normalized Gate Pitch a Verage C Hannel Stress [M Pa]mentioning

confidence: 96%

Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs

Kim

Jain

Rhee

et al. 2010

2010 International Conference on Simulation of Semiconductor Processes and Devices

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The impact of gate-pitch scaling on device internal and external resistance is examined by advanced process and device modeling including distributed contact resistance model, mechanical stress and Monte Carlo (MC)-based stressdependent mobility model. The contact resistance components and their major parameters in sub-50nm contact regime are analyzed by TCAD and transmission line modeling (TLM). The calibration method for the stress-induced channel mobility and the external resistance is proposed using R on -L gate measurements of 32nm-node devices with different gatepitches. The significant performance degradation due to simple gate-pitch scaling is predicted for 20nm-node technology with sub-100nm gate-pitch. I. INTRDUCTIONStress engineering using etch stop liner (ESL) or dual stress liner (DSL) has become one of the main performance element to enhance channel mobility in recent nano-meter scale CMOS technologies [1]. However, as the gate pitch aggressively scales down into sub-100nm regime with continuous technology scaling beyond 32nm-node [2], the two primary concerns and critical challenges for the device performance are being addressed as illustrated in Fig. 1: First, the stress effect associated with liner can be weakened by the narrower distance between neighboring gates which can be the effective space for transferring liner stress into channel. Second, this narrowed gate-space would lead to significant increase in the external resistance, R ext , since the silicide contact length, L con becomes shorter than the contact transfer length and hence will directly increase the contact resistance, R co [3].In this paper, the impact of gate-pitch scaling on device performance element is examined by advanced process and device modeling including the distributed contact resistance model, mechanical stress and Monte Carlo (MC)-based stress-dependent mobility model. The gate length dependence and the pitch dependence and tensile liner stress effect on the internal and external resistances are correlated to measured R on -L gate response of 32nm-node NFETs and applied for 20nm-node technology performance prediction. Effective Space for Contact Resistance and Liner StressL con L gate Gate Pitch Simulation Structure Stress Liner Gate Silicide Figure 1. Schematic illustration of device structure with gate pitch. The effective space transferring liner stress into channel and the silicide contact resistance are scaled with the aggressive shrink of gate-pitch. II. TCAD MODELING AND ANALYSISTCAD process and device modeling using Sentaurus process and device simulator are developed to reflect IBM 32nm high-k/metal gate bulk CMOS technology. Starting from the advanced calibration models, the basic 1-dimentional (1D) and 2-dimentional (2D) parameters are calibrated using experimental data such as device geometries, doping profiles and long and short channel electrical data. A. Impact on Contact ResistanceIn order to understand the gate-pitch dependence on contact resistance, the detailed silicide contact parameter study is ...

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“…3 To address this problem, NiSi is now being used in state-of-theart CMOS devices in the form of a (Ni,Pt)Si ternary alloy. 4 Alloying Pt with NiSi combats the poor morphology and phase stability problems encountered with NiSi films that usually start to agglomerate below 600 C and transform to NiSi 2 above 700 C. 5,6 However, NiSi 2 formation becomes spontaneous and is inevitable when the silicide formation (without Pt) occurs in extremely down-scaled contact windows. 7,8 In the most advanced CMOS technologies, the traditional polycrystalline-silicon gates are replaced with pure a) Electronic mail: zhiwei.zhu@angstrom.uu.se b) Author to whom correspondence should be addressed; electronic mail: dongpingwu@fudan.edu.cn metals with appropriate work functions in order to achieve the desired threshold voltages for both conduction polarities.…”

Section: Introductionmentioning

confidence: 99%

Extensive Raman spectroscopic investigation of ultrathin Co1−xNixSi2 films grown on Si(100)

Piao¹,

Zhu²,

Gao³

et al. 2012

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

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Ultrathin silicide films were formed by starting from 1–8 nm thick Co1−xNix (x = 0, 0.25, 0.5, 0.75, and 1) at 350 °C–900 °C. For each composition x, there exists a critical thickness above which the transition temperature from monosilicides CoSi and NiSi to a disilicide-like phase increases with increasing film thickness. Below this thickness, the disilicide phase seems to form without exhibiting the monosilicides within the detection resolution limits of transmission electron microscopy and Raman spectroscopy. Raman spectroscopic analysis seems to indicate that Ni could be dissolved in the CoSi lattice to a certain fraction despite the fact that CoSi and NiSi are distinct with different crystallographic structures. Moreover, the disorder-induced Raman scattering in NiSi2 is found to be enhanced by Co incorporation. The observed annealing behaviors are attributed to variations in free energy change for phase transition caused by differences in metal thickness.

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Extendibility of NiPt Silicide Contacts for CMOS Technology Demonstrated to the 22-nm Node

Cited by 25 publications

References 3 publications

Nucleation and diffusion during growth of ternary Co1−xNixSi2 thin films studied by complementary techniques in real time

Nucleation and diffusion during growth of ternary Co1−xNixSi2 thin films studied by complementary techniques in real time

Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs

Extensive Raman spectroscopic investigation of ultrathin Co1−xNixSi2 films grown on Si(100)

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