Extend orthogonal Latin square codes for 32-bit data protection in memory applications

Liu, Shanshan; Xiao, Liyi; Mao, Zhigang

doi:10.1016/j.microrel.2016.06.002

Cited by 16 publications

(9 citation statements)

References 20 publications

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“…En este sentido, hemos comparado diferentes parámetros de nuestro código con una serie de ECC bien conocidos, con tamaño de datos iguales (32 bits) y capacidades de corrección similares (ECC capaces de corregir el 100% de los errores simples y dobles aleatorios). Específicamente, hemos usado los códigos OLS (55, 32) [25] y BCH (44, 32) [15]. Hemos seleccionado estos ECC porque implementan diferentes métodos en la corrección de errores, aunque su distancia d = 5 es inferior a la del código propuesto.…”

Section: Evaluación De Los Codificadores Y Decodificadoresunclassified

Design, Implementation and Evaluation of a Low Redundant Error Correction Code

Gracia-Morán

Saiz-Adalid

Calvo

et al. 2021

IEEE Latin Am. Trans.

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The continuous increment in the integration scale of CMOS technology has provoked an augment in the fault rate. Particularly, a single particle hit in a storage element (such as memory or registers) can provoke a single error in a memory cell (known as Single Cell Upsets or SCU), as well as simultaneous errors in more than one memory cell (known as Multiple Cell Upsets or MCU). A common method to tolerate this type of errors is the use of Error Correction Codes (ECC). However, the addition of an ECC introduces a series of overheads: silicon area, power consumption and delay overheads of encoding and decoding circuits, as well as several extra bits added to detect and/or correct errors. An ECC can be designed focusing on different parameters: low redundancy, low delay, error coverage, etc. The design of ECC is a very active field, and ECC with different properties are continuously proposed. However, usually, these proposals only present the ECC, not showing what happens when they are included in a microprocessor. The idea of this paper is twofold. First, we present the design of an ECC whose main characteristic is its low number of code bits (low redundancy). This ECC adds 15 redundant bits to a 32-bit data word to form a (47, 32) ECC able to correct single and doble errors, and to detect triple errors. Second, we also study the overheads that this ECC introduces when added to a RISC microprocessor, comparing it with some other well-known ECC.

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Section: Evaluación De Los Codificadores Y Decodificadoresunclassified

Design, Implementation and Evaluation of a Low Redundant Error Correction Code

Gracia-Morán

Saiz-Adalid

Calvo

et al. 2021

IEEE Latin Am. Trans.

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“…In the error correction structure, extra bits add to each data stored in the memories. The different types of ECCs, such as orthogonal latin square (OLS), low density parity check (LDPC), and Hamming, do memory protection 18 …”

Section: Performance Analysismentioning

confidence: 99%

Low‐voltage and high‐speed stand‐alone multiple‐input complex gates for error correction coding applications

Rafiee

Ghaznavi‐Ghoushchi

2020

Circuit Theory & Apps

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Summary This paper presents two low‐voltage high‐speed shallow‐depth current mode logic (CML) topologies. The number of stacked transistors of these proposed structures decreases between VDD to GND. Reduce stacks in proposed gates enhance the circuit to operate at lower supply voltages. Therefore, the proposed logic causes to use of a stand‐alone multiple‐input gate instead of a low‐input gate. The use of decomposing multiple‐input gate for some input series causes error in the output of the circuit. In advanced technologies with size scaling down, the reliability and correctness of data in memories are essential issues. Error correction codes (ECCs) are used for protecting memories against faults. Reducing power consumption with preserving speed is vital in the design of ECCs. The units of ECCs are composed of multiple‐input gates; hence, using a low‐voltage high‐performance structure is required. The essential properties of the proposed logic are low‐voltage and high‐speed operation modes. It also gains in delay improvement of the proposed structure and multiple‐tailed current mode logic (MTCML) than source‐coupled logic (SCL) about 27% and 21% in the low‐voltage design. The final power delay product (PDP) of proposed logic and MTCML is improved by about 14% and 11% than SCL.

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“…• DEC Orthogonal Latin Square [25]: the (20, 8) code described in [33], the (32, 16) code shown in [34], the (55, 32) code presented in [35], and the (96, 64) code defined in [36].…”

Section: Codes For Longer Data Wordsmentioning

confidence: 99%

Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection

et al. 2019

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Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single error correction-double error detection (SEC-DED) codes. ECCs are traditionally designed to minimize the number of redundant bits, as they are added to each word in the whole memory. Nevertheless, using an ECC introduces encoding and decoding latencies, silicon area usage and power consumption. In other computer units, these parameters should be optimized, and redundancy would be less important. For example, protecting registers against errors remains a major concern for deep sub-micron systems due to technology scaling. In this case, an important requirement for register protection is to keep encoding and decoding latencies as short as possible. Ultrafast error control codes achieve very low delays, independently of the word length, increasing the redundancy. This paper summarizes previous works on Ultrafast codes (SEC and SEC-DED), and proposes new codes combining double error detection and adjacent error correction. We have implemented, synthesized and compared different Ultrafast codes with other state-of-the-art fast codes. The results show the validity of the approach, achieving low latencies and a good balance with silicon area and power consumption. INDEX TERMS Adjacent error correction, double error detection, error control codes, fast codes, reliability.

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Extend orthogonal Latin square codes for 32-bit data protection in memory applications

Cited by 16 publications

References 20 publications

Design, Implementation and Evaluation of a Low Redundant Error Correction Code

Design, Implementation and Evaluation of a Low Redundant Error Correction Code

Low‐voltage and high‐speed stand‐alone multiple‐input complex gates for error correction coding applications

Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection

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