Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection

Abstract

Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single error correction-double error detection (SEC-DED) codes. ECCs are traditionally designed to minimize the number of redundant bits, as they are added to each word in the whole memory. Nevertheless, using an ECC introduces encoding and decoding latencies, silicon area usage and power consumption. In other computer units, these parameters should be optimized, and redundancy would be less important. For example, protecting registers against errors remains a major concern for deep sub-micron systems due to technology scaling. In this case, an important requirement for register protection is to keep encoding and decoding latencies as short as possible. Ultrafast error control codes achieve very low delays, independently of the word length, increasing the redundancy. This paper summarizes previous works on Ultrafast codes (SEC and SEC-DED), and proposes new codes combining double error detection and adjacent error correction. We have implemented, synthesized and compared different Ultrafast codes with other state-of-the-art fast codes. The results show the validity of the approach, achieving low latencies and a good balance with silicon area and power consumption. INDEX TERMS Adjacent error correction, double error detection, error control codes, fast codes, reliability.

Reducing the Overhead of BCH Codes: New Double Error Correction Codes

“…Frequently, ECC designers can achieve these objectives by increasing the number of parity bits. Depending on the application, it could be an interesting alternative (e.g., [18]). However, this is not a good idea when protecting memories, as all redundant bits must be stored per individual word in the whole memory, leading to a much higher silicon area being occupied and more power being consumed by the memory circuitry.…”

Lower complexity error location detection block of adjacent error correcting decoder for SRAMs

“…The area complexity of the decoder has been reduced by the first technique and decoder's delay has been minimised by the second technique. Recently, a class of ECCs with single and multiple adjacent errror correction capability has been presented by Adalid et al in [28]. The main advantages of these codes are their ultra-fast encoding and decoding operations.…”

“…Recently, a class of ECCs with single and multiple adjacent errror correction capability has been presented by Adalid et al in [28]. The main advantages of these codes are their ultra‐fast encoding and decoding operations.…”

“…Also K‐map has been employed to reduce the delay further in decoding circuits. The decoding circuitry needed for the codes presented in [28] is very much simplified as much higher number of do not care conditions are available compared to the number of bits to be corrected due to the increased redundancy. So the codes presented in [28] achieve ultra‐fast operations in the expense of redundancy.…”

“…The decoding circuitry needed for the codes presented in [28] is very much simplified as much higher number of do not care conditions are available compared to the number of bits to be corrected due to the increased redundancy. So the codes presented in [28] achieve ultra‐fast operations in the expense of redundancy. However, this scheme is most suitable for the applications where redundancy is not a constraint like protection of register files compared to SRAMs applications.…”