Exploring power management in multi-core systems

Bergamaschi, Reinaldo A.; Han, Guoling; Buyuktosunoglu, Alper; Patel, Hiren; Nair, Indira; Dittmann, Gero; Janssen, Geert; Dhanwada, Nagu; Hu, Zhigang; Bose, Pradip; Darringer, John A.

doi:10.1109/aspdac.2008.4484043

Cited by 32 publications

(21 citation statements)

References 19 publications

(25 reference statements)

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“…In prior work [7][8][9], we describe some of the promising multi-core power management algorithms that yield significant benefit, when dealing with a specific control knob: that of dynamic voltage and frequency scaling (DVFS). Dynamic power gating (DPG) algorithms [10,11] are targeted to reduce power by cutting off the power supply to unused resources.…”

Section: A Dynamic Voltage-frequency Scaling and Power Gatingmentioning

confidence: 99%

“…Experimental evaluation of the power-performance benefit of such multi-core DVFS algorithms (e.g. [7][8][9]) is essential, in order to design the power management architecture (and micro-architecture) for such systems. Figure 2 shows the power-performance characteristics of a multi-core processor with a global power controller.…”

Section: A Dynamic Voltage-frequency Scaling and Power Gatingmentioning

confidence: 99%

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Power management of multi-core chips: Challenges and pitfalls

Bose¹,

Buyuktosunoglu²,

Darringer³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Modern processor systems are equipped with onchip or on-board power controllers. In this paper, we examine the challenges and pitfalls in architecting such dynamic power management control systems. A key question that we pose is: How to ensure that such managed systems are "energysecure" and how to pursue pre-silicon modeling to ensure such security? In other words, we address the robustness and security issues of such systems. We discuss new advances in energy-secure power management, starting with an assessment of potential vulnerabilities in systems that do not address such issues up front.

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Section: A Dynamic Voltage-frequency Scaling and Power Gatingmentioning

confidence: 99%

Section: A Dynamic Voltage-frequency Scaling and Power Gatingmentioning

confidence: 99%

Power management of multi-core chips: Challenges and pitfalls

Bose¹,

Buyuktosunoglu²,

Darringer³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

show abstract

“…It means designers will face the challenge of processor power consumption and heat dissipation problem. Because higher temperature can increase leakage current, thus may lead to degradation in performance [1]. As a result, the processinduced leakage current variations become a big concern.…”

Section: Introductionmentioning

confidence: 99%

Framework for statistical analysis of homogeneous multicore power grid networks

Liu

Fan

2009

2009 IEEE 8th International Conference on ASIC

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In this paper, we propose a framework to analyze the large-scaled multicore power grid network statistically by first building a simplified multicore power supply distribution model. We then apply the Modified Nodal Analysis (MNA) method on a simplified power gird circuit. Under such a framework, most statistical approaches, including Monte Carlo (MC), Importance Sampling, and Stochastic Spectrum Analysis, can be applied to analyze the processinduced variation of homogeneous multicore power grid networks. In the experiment, we focus on the subthreshold leakage current variations, which are modeled as lognormal distribution random variables, by using MC approach as an example to demonstrate the feasibility of such a framework. 1

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“…We exclude from our analysis of other software configurable parameters such as the frequency and the voltage associated with each system processor (Dynamic Voltage and Frequency Scaling, DVFS [2], [3]) for the following reasons: a) they are orthogonal to our methodology, b) our focus is on the actual performance and power trade-offs which can be achieved with pure task-level parallelism.…”

mentioning

confidence: 99%

A design space exploration methodology supporting run-time resource management for multi-processor Systems-on-chip

Mariani¹,

Palermo

Silvano

et al. 2009

2009 IEEE 7th Symposium on Application Specific Processors

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Abstract-Application Specific multi-processor Systems-onchip are currently designed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned either at design-time or at run-time, to provide the best trade-offs in terms of the selected system figures of merit (such as power and throughput) for a dynamic application-specific workload. Among the design-time (hardware) configurable parameters we can find the memory sub-system configuration (e.g. cache size and associativity) and other architectural parameters such as the instruction-level parallelism of the system processors. Among the run-time (software) configurable parameters we can find the overall degree of task-level parallelism associated with each application running on the chip. Typically, while the design-time exploration is performed in the early development stages for a set of static parameters, the tuning of the run-time parameters is performed dynamically by a runtime management software module after the system has been deployed.In this paper, we introduce a methodology for identifying a hardware configuration which is robust with respect to the variable workload scenario introduced by the run-time management. Moreover, the proposed methodology is aimed at providing useful information about the optimal operating points of the applications in terms of task-level parallelism. The proposed methodology is based on the NSGA-II evolutionary heuristic algorithm assisted by an Artificial Neural Network (ANN). We then introduce a run-time management policy capable to exploit the above information to maximize the performance of the system under power budget constraints.Experimental results show that the proposed technique is able to reduce the overall design space exploration time yet providing a near-optimal solution, in terms of hardware parameters, to enable an innovative and efficient run-time management policy 1 .

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Exploring power management in multi-core systems

Cited by 32 publications

References 19 publications

Power management of multi-core chips: Challenges and pitfalls

Power management of multi-core chips: Challenges and pitfalls

Framework for statistical analysis of homogeneous multicore power grid networks

A design space exploration methodology supporting run-time resource management for multi-processor Systems-on-chip

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