Power management of multi-core chips: Challenges and pitfalls

Bose,; Buyuktosunoglu,; Darringer,; Gupta, Rajiv; Healy,; Jacobson,; Nair,; Rivers,; Shin, Jae Hoon; Vega, J.; Weger,

doi:10.1109/date.2012.6176638

Cited by 24 publications

(9 citation statements)

References 20 publications

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“…The paper also analyzes possible "holes" (which may produce negative power savings) and proposes a guard mechanism to prevent them. Also related to robustness of power management in multi-core processors, Bose et al [5] provides a broad overview of the potential holes and introduce the idea of guarded power management.…”

Section: Related Workmentioning

confidence: 99%

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Vega¹,

Buyuktosunoglu²,

Hanson³

et al. 2013

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

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Dynamic power management features are now an integral part of processor chip and system design. Dynamic voltage and frequency scaling (DVFS), core folding and percore power gating (PCPG) are power control actuators (or "knobs") that are available in modern multi-core systems. However, figuring out the actuation protocol for such knobs in order to achieve maximum efficiency has so far remained an open research problem. In the context of specific system utilization dynamics, the desirable order of applying these knobs is not easy to determine.For complexity-effective algorithm development, DVFS, core folding and PCPG control methods have evolved in a somewhat decoupled manner. However, as we show in this paper, independent actuation of these techniques can lead to conflicting decisions that jeopardize the system in terms of power-performance efficiency. Therefore, a more robust coordination protocol is necessary in orchestrating the power management functions. Heuristics for achieving such coordinated control are already becoming available in server systems. It remains an open research problem to optimally adjust power and performance management options at runtime for a wide range of time-varying workload applications, environmental conditions, and power constraints.This research paper contributes a novel approach for a systematically architected, robust, multi-knob power management protocol, which we empirically analyze on live server systems. We use a latest generation POWER7+ multi-core system to demonstrate the benefits of our proposed new coordinated power management algorithm (called PAMPA). We report measurement-based analysis to show that PAMPA achieves comparable power-performance efficiencies (relative to a baseline decoupled control system) while achieving conflict-free actuation and robust operation.

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Section: Related Workmentioning

confidence: 99%

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Vega¹,

Buyuktosunoglu²,

Hanson³

et al. 2013

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

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“…The time complexity of the search increases exponentially in the number of cores and, thus, their approach does not scale to large core counts. More recent works (e.g., [15], [16]) have improved on Isci's exhaustive search, but never addressed the combination of CPU and memory DVFS. Moreover, most prior works attempt to maximize instruction throughput, which causes an unfair power allocation across applications (CPU-bound applications tend to get a larger share of the power).…”

Section: Introductionmentioning

confidence: 99%

FastCap: An efficient and fair algorithm for power capping in many-core systems

Liu

Cox

Deng

et al. 2016

2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Future servers will incorporate many active lowpower modes for different system components, such as cores and memory. Though these modes provide flexibility for power management via Dynamic Voltage and Frequency Scaling (DVFS), they must be operated in a coordinated manner. Such coordinated control creates a combinatorial space of possible power mode configurations. Given the rapid growth of the number of cores, it is becoming increasingly challenging to quickly select the configuration that maximizes the performance under a given power budget. Prior power capping techniques do not scale well to large numbers of cores, and none of those works has considered memory DVFS.In this paper, we present FastCap, our optimization approach for system-wide power capping, using both CPU and memory DVFS. Based on a queuing model, FastCap formulates power capping as a non-linear optimization problem where we seek to maximize the system performance under a power budget, while promoting fairness across applications. Our FastCap algorithm solves the optimization online and efficiently (low complexity on the number of cores), using a small set of performance counters as input. To evaluate FastCap, we simulate it for a many-core server running different types of workloads. Our results show that FastCap caps power draw accurately, while producing better application performance and fairness than many existing CPU power capping methods (even after they are extended to use of memory DVFS as well).

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“…In the server systems [14] and multi-core processors [15], a variety of methods have been proposed [16] for securing power gating with guard mechanisms. In the field of WSNs, researchers attempt to fine methods to solve barrage attack and sleep deprivation attack.…”

Section: Introductionmentioning

confidence: 99%

Attack-resistant power management scheme for wireless sensor network

Tsai

et al. 2015

2015 International Conference on Advanced Robotics and Intelligent Systems (ARIS)

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Wireless sensor networks (WSNs) which powered by batteries are widely used in military, healthcare, and scientific environments. One important challenge for setting WSN is the energy problem. Power management is one of efficient solutions for such problem and must be taken into account at all levels of the WSN. However, the power management may be out of action when the WSN suffers malicious attacks. In this paper, an Attack-Resistant Power Management (A-RPM for short) scheme is proposed for WSN to deal with the energy problem and prolong the operating time of sensor nodes as well as coordinators. Most importantly, the A-RPM is still effectual when WSN under malicious attacks such as denial-of-service attack. The A-RPM efficiently turns WSN nodes into sleep mode, which consumes less energy, but requires higher latency to awaken, when these nodes are idle and wake them up when necessary. A token based operating mode transition policy is developed to control the power of WSN nodes. Our simulation result shows that the A-RPM effectively reduces power consumption up to 16.35% when the network suffer malicious attacks compared with that of the standard power management scheme.

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Power management of multi-core chips: Challenges and pitfalls

Cited by 24 publications

References 20 publications

Crank it up or dial it down

Crank it up or dial it down

FastCap: An efficient and fair algorithm for power capping in many-core systems

Attack-resistant power management scheme for wireless sensor network

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