Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When Do Smaller Less Reliable Devices Make Sense?

Zykov, A.V.; Veciana, Gustavo de

doi:10.1109/dft.2008.30

Cited by 4 publications

(2 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As a result, complete connectivity among all the components will not be viable. Hence, the future systems will be characterized by a high level of complexity with limited connectivity [2], [5]. In addition, dark silicon phenomenon is expected to be more prominent among the future nano devices [6].…”

Section: Introductionmentioning

confidence: 99%

Decentralized self-balancing systems

Banerjee

Zhao

Rao

et al. 2013

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)

View full text Add to dashboard Cite

The transition to Nano-scale devices is expected to open the way for highly complex parallel systems. However, decreased reliability and strict interconnect limitations are two important challenges that the devices need to overcome. To do so, such systems have to adapt to the changing workload and faults, employing decentralized protocols to coordinate among the many components. In this paper, we investigate algorithms for evenly distributing resources among locally connected components, so that the system can dynamically self-balance as the availability of resources changes. We propose two efficient Decentralized Protocols that achieve near-optimal resource distributions. The protocols are scalable and guarantee the desired fair distribution regardless of the interconnect topology.

show abstract

Section: Introductionmentioning

confidence: 99%

Decentralized self-balancing systems

Banerjee

Zhao

Rao

et al. 2013

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)

View full text Add to dashboard Cite

show abstract

“…It has been observed experimentally that the relationship between terminals and devices follows a power law with exponent r. This exponent depends on the design style and remains stable for different partitions of the circuit. Therefore, if we assume hierarchical consistency as previous work [85], we can use this property in cross-layer systems to estimate the amount of interconnects at any particular layer and decompose the global error probability to perform our analysis. Indeed, let us consider a cross-layer system of D s devices, see Figure 7.…”

Section: Analysis Methodsmentioning

confidence: 99%

Variability-aware architectures based on hardware redundancy for nanoscale reliable computation

Aymerich Capdevila

View full text Add to dashboard Cite

During the last decades, human beings have experienced a significant enhancement in the quality of life thanks in large part to the fast evolution of Integrated Circuits (IC). This unprecedented technological race, along with its significant economic impact, has been grounded on the production of complex processing systems from highly reliable compounding devices. However, the fundamental assumption of nearly ideal devices, which has been true within the past CMOS technology generations, today seems to be coming to an end. In fact, as MOSFET technology scales into nanoscale regime it approaches to fundamental physical limits and starts experiencing higher levels of variability, performance degradation, and higher rates of manufacturing defects. On the other hand, ICs with increasing number of transistors require a decrease in the failure rate per device in order to maintain the overall chip reliability. As a result, it is becoming increasingly important today the development of circuit architectures capable of providing reliable computation while tolerating high levels of variability and defect rates. The main objective of this thesis is to analyze and propose new fault-tolerant architectures based on redundancy for future technologies. Our research is founded on the principles of redundancy established by von Neumann in the 1950s and extends them to three new dimensions: 1. Heterogeneity: Most of the works on fault-tolerant architectures based on redundancy assume homogeneous variability in the replicas like von Neumann's original work. Instead, we explore the possibilities of redundancy when heterogeneity between replicas is taken into account. In this sense, we propose compensating mechanisms that select the weighting of the redundant information to maximize the overall reliability. 2. Asynchrony: Each of the replicas of a redundant system may have associated different processing delays due to variability and degradation; especially in future nanotechnologies. If we design our system to work locally in asynchronous mode then we may consider different voting policies to deal with the redundant information. Depending on how many replicas we collect before taking a decision we can obtain different trade-off between processing delay and reliability. We propose a mechanism for providing these facilities and analyze and simulate its operation. 3. Hierarchy: Finally, we explore the possibilities of redundancy applied at different hierarchy layers of complex processing systems. We propose to distribute redundancy across the various hierarchy layers and analyze the benefits that can be obtained. Drawing on the scenario of future ICs technologies, we push the concept of redundancy to its fullest expression through the study of realistic nano-device architectures. Most of the redundant architectures considered so far do not face properly the era of Terascale Computing and the nanotechnology trends. Since von Neumann applied for the first time redundancy at electronic circuits, never until now effects as common in nanoelectronics as degradation and interconnection failures have been treated directly from the standpoint of redundancy. In this thesis we address in a comprehensive manner the reliability of digital processing systems in the upcoming technology generations.

show abstract

Study on the optimal distribution of redundancy effort in cross-layer reliable architectures

Aymerich

Rubio

2013

2013 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013)

View full text Add to dashboard Cite

This paper presents a comprehensive approach to the smart application of redundancy techniques in multiple-layer hierarchical systems. Computing systems today are rapidly evolving into increasingly complex structures with an ever-increasing number of components. Moreover, future technology generations are expected to have associated lower levels of quality. For these reasons, it is emerging nowadays a renewed interest in the development of reliable architectures. In this work we delve into this topic putting special emphasis on the system hardware hierarchy. We analyze the advantages in terms of reliability of distributing redundancy effort in cross-layer systems. We base our analysis on a general fault model that takes into account both devices and interconnections. Using the Rent's Law we relate the number of devices and interconnections for different configurations of redundancy and compare the global error probability. Our results provide meaningful information about the benefits that can be achieved by properly choosing the system layer at which to apply redundancy, and if applicable, the optimal distribution of redundancy effort through the system layers. © 2013 IEEE.Peer ReviewedPostprint (published version

show abstract

Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When Do Smaller Less Reliable Devices Make Sense?

Abstract: It is widely recognized that device and interconnect fabrics at the nanoscale will be character-

Cited by 4 publications

References 14 publications

Decentralized self-balancing systems

Decentralized self-balancing systems

Variability-aware architectures based on hardware redundancy for nanoscale reliable computation

Study on the optimal distribution of redundancy effort in cross-layer reliable architectures

Contact Info

Product

Resources

About