Exploration of Lattice Reduction Aided Soft-Output MIMO Detection on a DLP/ILP Baseband Processor

Ahmad, Ubaid; Li, Min; Appeltans, Raf; Nguyen, Hoang Duy; Amin, Amir; Dejonghe, Antoine; Perre, Liesbet Van der; Lauwereins, Rudy; Pollin, Sofie

doi:10.1109/tsp.2013.2279773

Cited by 8 publications

(4 citation statements)

References 33 publications

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“…The programmable VLIW core [8] takes less clock cycle and flexible. The implementation consisted of not only LR, but also QR decomposition and detection also.…”

Section: Resultsmentioning

confidence: 99%

“…Two SFUs for µ calculation and size reduction are designed according to [8]. These SFUs are single-cycle and multiplierless.…”

Section: A Special Function Unitsmentioning

confidence: 99%

“…A customized very long instruction word (VLIW) processor is implemented in [8] for the LR. We take different approach and design a customized multiprocessor based on the transport triggered architecture (TTA) paradigm.…”

Section: Introductionmentioning

confidence: 99%

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A customized lattice reduction multiprocessor for MIMO detection

Shahabuddin

Janhunen

Khan

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Lattice reduction (LR) is a preprocessing technique for multiple-input multiple-output (MIMO) symbol detection to achieve better bit error-rate (BER) performance. In this paper, we propose a customized homogeneous multiprocessor for LR. The processor cores are based on transport triggered architecture (TTA). We propose some modification of the popular LR algorithm, Lenstra-Lenstra-Lovász (LLL) for high throughput. The TTA cores are programmed with high level language. Each TTA core consists of several special function units to accelerate the program code. The multiprocessor takes 187 cycles to reduce a single matrix for LR. The architecture is synthesized on 90 nm technology and takes 405 kgates at 210 MHz.

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“…The programmable VLIW core [8] takes less clock cycle and flexible. The implementation consisted of not only LR, but also QR decomposition and detection also.…”

Section: Resultsmentioning

confidence: 99%

“…Two SFUs for µ calculation and size reduction are designed according to [8]. These SFUs are single-cycle and multiplierless.…”

Section: A Special Function Unitsmentioning

confidence: 99%

See 1 more Smart Citation

A customized lattice reduction multiprocessor for MIMO detection

Shahabuddin

Janhunen

Khan

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…It consists of a VLIW processor and a coarsegrained reconfigurable matrix. In [29], an MIMO detector for ADRES-based processor is proposed, which has a 256b SIMD datapath consisting of eight lanes, where each lane has complex-valued arithmetic units. However, their multitree selective spanning-based MIMO detection supports only hard-bit decision output, not soft-bit output.…”

Section: Related Workmentioning

confidence: 99%

LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor

Kultala

Viitanen²,

Berg

et al. 2019

IEEE Trans. VLSI Syst.

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This paper proposes a single instruction multiple data (SIMD) processor, which is programmed with high-level OpenCL language. The low-power processor is customized for executing multiple-input-multiple-output (MIMO) detection algorithms at a high performance while consuming very little power making it suitable for software-defined radio (SDR) applications. The novel combination of SIMD operations on a transport programmed multicore datapath allows saving power on both the execution front end and the back end, leading to very good energy efficiency with a compiler programmable design. We demonstrate the feasibility of the architecture with the layered orthogonal lattice detector and minimum mean-squareerror MIMO algorithms, which can be used as a software-defined radio implementation of the 3GPP local thermal equilibrium r11 standard. Compared to other state-of-the-art SDR architectures, the proposed design adds features that improve programmer productivity with an insignificant power and area impact.

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