A customized lattice reduction multiprocessor for MIMO detection

Shahabuddin, Shahriar; Janhunen, Janne; Khan, Zaheer; Juntti, Markku; Ghazi, Amanullah

doi:10.1109/iscas.2015.7169312

Cited by 14 publications

(4 citation statements)

References 13 publications

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“…Performance of linear detectors can be improved by modifying the ill-conditioned channel matrix to be more orthogonal using LRA methods [215], [216]. Figure 8 shows the decision regions before and after the LRA.…”

Section: B Lattice Reduction-aided Algorithmsmentioning

confidence: 99%

Massive MIMO Detection Techniques: A Survey

Albreem

Juntti

Shahabuddin

2019

IEEE Commun. Surv. Tutorials

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347

229

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Section: B Lattice Reduction-aided Algorithmsmentioning

confidence: 99%

Massive MIMO Detection Techniques: A Survey

Albreem

Juntti

Shahabuddin

2019

IEEE Commun. Surv. Tutorials

Self Cite

347

229

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“…During first 64 cycles required to load the S − G memory, we compute the inverse of the diagonal elements with Newton-Raphson method [7]. The inverse 1/x can be computed in an iterative manner with Newton-Raphson method as…”

Section: Vlsi Architecturementioning

confidence: 99%

FPGA Implementation of Stair Matrix based Massive MIMO Detection

Shahabuddin

Albreem²,

Shahabuddin

et al. 2021

2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS)

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Approximate matrix inversion based methods is widely used for linear massive multiple-input multiple-output (MIMO) received symbol vector detection. Such detectors typically utilize the diagonally dominant channel matrix of a massive MIMO system. Instead of diagonal matrix, a stair matrix can be utilized to improve the error-rate performance of a massive MIMO detector. In this paper, we present very large-scale integration (VLSI) architecture and field programmable gate array (FPGA) implementation of a stair matrix based iterative detection algorithm. The architecture supports a base station with 128 antennas, 8 users with single antenna, and 256 quadrature amplitude modulation (QAM). The stair matrix based detector can deliver a 142.34 Mbps data rate and reach a clock frequency of 258 MHz in a Xilinx Virtex-7 FPGA. The detector provides superior error-rate performance and higher scaled throughput than most contemporary massive MIMO detectors.

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“…A custom multicore TTA processor for lattice reduction is proposed in [31]. The system is based on a pipelined multicore, where each core executes each stage of their multistage algorithm.…”

Section: Related Workmentioning

confidence: 99%

LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor

Kultala

Viitanen²,

Berg

et al. 2019

IEEE Trans. VLSI Syst.

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This paper proposes a single instruction multiple data (SIMD) processor, which is programmed with high-level OpenCL language. The low-power processor is customized for executing multiple-input-multiple-output (MIMO) detection algorithms at a high performance while consuming very little power making it suitable for software-defined radio (SDR) applications. The novel combination of SIMD operations on a transport programmed multicore datapath allows saving power on both the execution front end and the back end, leading to very good energy efficiency with a compiler programmable design. We demonstrate the feasibility of the architecture with the layered orthogonal lattice detector and minimum mean-squareerror MIMO algorithms, which can be used as a software-defined radio implementation of the 3GPP local thermal equilibrium r11 standard. Compared to other state-of-the-art SDR architectures, the proposed design adds features that improve programmer productivity with an insignificant power and area impact.

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A customized lattice reduction multiprocessor for MIMO detection

Cited by 14 publications

References 13 publications

Massive MIMO Detection Techniques: A Survey

Massive MIMO Detection Techniques: A Survey

FPGA Implementation of Stair Matrix based Massive MIMO Detection

LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor

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