LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor

Abstract

This paper proposes a single instruction multiple data (SIMD) processor, which is programmed with high-level OpenCL language. The low-power processor is customized for executing multiple-input-multiple-output (MIMO) detection algorithms at a high performance while consuming very little power making it suitable for software-defined radio (SDR) applications. The novel combination of SIMD operations on a transport programmed multicore datapath allows saving power on both the execution front end and the back end, leading to very good energy efficiency with a compiler programmable design. We demonstrate the feasibility of the architecture with the layered orthogonal lattice detector and minimum mean-squareerror MIMO algorithms, which can be used as a software-defined radio implementation of the 3GPP local thermal equilibrium r11 standard. Compared to other state-of-the-art SDR architectures, the proposed design adds features that improve programmer productivity with an insignificant power and area impact.

Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode

“…Reducing both the amount of register file ports and interconnect connectivity is important with wide processor architectures, as otherwise they quickly hit the ILP complexity wall [25] due to the amount of connectivity on the processor datapath. TTAs' modular structure allows heavy pruning of the interconnection network due to programmer-directed operand transportations, which enables easy scaling from high-performance [26] to small energy-efficient TTA designs [27]. Figure 2 describes an example of a TTA instruction template for an architecture with five busses.…”

Synthetic Aperture Radar Algorithms on Transport Triggered Architecture Processors using OpenCL

“…The proposed architecture shows a 14 × reduction in cycles, compared to a Texas Instruments C66x. Aside from that, there are some reports of TTAs being used for softwaredefined radio (SDR) implementation of mobile communication standards [12]- [14]. The TTA described in [13], which is optimized for decoding of polar codes, is reported to outperform state-of-the-art ASIP implementations fivefold in throughput while consuming an order of magnitude less energy.…”

“…They find that their TTA implementation achieves a 1.85 to 10.73 better mW/MHz rating than comparable architectures. The "LordCore", a TTA processor for the decoding of Turbo-Codes [14] is said to outperform GPU-based implementations by three orders of magnitude in the performance/power ratio. Compared to fixed-function implementations of the algorithm, the TTA implementation requires more power, but "[the] results show that the energy Fig.…”

“…The colored arrows indicate data transports that are executed simultaneously. Reproduced from [14]. penalty paid by programmability can be made very small" [14].…”

Feasibility Test of Raspberry Pi Based Spectrum Analyzer and Transfer Level Register-Software Defined Radio as Learning Media for Frequency Measurement

“…For programmability and reconfiguration purposes, field programmable gate arrays (FPGAs) are the platform of choice for implementing most SDR concepts (Balakrishnan et al, 2019). SDR processors are challenging to design because multiple-input multipleoutput (MIMO) orthogonal frequency division multiplexing (OFDM) links require tremendous processing power (Kultala et al, 2019).…”