Exploration and Device Optimization of Dielectric–Ferroelectric Sidewall Spacer in Negative Capacitance FinFET

Estimation of performance degradation due to interface traps in the gate and spacer stack of NC-FinFET

“…The calibration procedure adopted for a 20 nm channel length (L G ) and 8 nm thickness (t FIN ) NC FinFET is designed using Sentaurus TCAD [11,23] and is described in section 2. The simulation framework basically comprises the appropriate tuning of device dimensions, metal gate work function, source/drain (S/D) underlap doping and resistances, in order to calibrate the reference baseline structure against the experimental data of a 14 nm node FinFET (figure 1(a)) [24].…”

“…In recent times, the introduction of high-k/FE spacers in underlap devices has garnered substantial interest as they impact the device characteristics by enhancing the gate-source/drain sidewall fields [7]. The use of optimized spacer configuration and permittivity in NCFETs boost the driving capability by exercising control over the outer fringing fields and parasitic capacitances that directly affect the capacitance matching phenomenon [8][9][10][11][12][13].…”

Buried interfacial gate oxide for tri-gate negative-capacitance fin field-effect transistors: approach and investigation

“…Finally, in figure 1(b), the improvement in the device performance is presented, which is obtained for the NC-FinFET at different drain biases. The details of the calibration procedure are discussed in [11,13].…”

“…This phenomenon leads to a progression in the sub-threshold characteristics and improved short channel characteristics, such as DIBL, V th rolloff, etc. For conventional devices, increasing the drain bias lowers the potential barrier, referred to as DIBL, whereas, in NC-FinFET, there is a rise in the drain barrier, also known as negative DIBL, occurring due to the negative differential resistance (NDR) effect [13,25,26]. In this work, the proposed NC-FinFET holds an average value of output conductance (g ds ) and showcases a low NDR effect (see figures 6(b) and (c)), leading to a positive DIBL index as shown in figure 5(a).…”

“…Several studies have been conducted to date to increase the performance of NC-based FETs and FinFETs, respectively. The incorporation of device engineering approaches, such as work function variability [8,9], material-structure evaluation [8,9], and spacer engineering [10][11][12][13], among others, has been published in recent years. However, the use of such variable permittivity spacers lowers the carrier mobility through the trap formation caused by Coulombic scattering [14] and affects circuit delays due to the increased fringe capacitance [15].…”